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https://github.com/VLSIDA/OpenRAM.git
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Test more single level col mux configs
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@@ -7,7 +7,7 @@
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# All rights reserved.
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#
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from testutils import *
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import sys,os
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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@@ -25,6 +25,14 @@ class single_level_column_mux_test(openram_test):
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OPTS.num_w_ports = 0
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globals.setup_bitcell()
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debug.info(1, "Testing sample for 2-way column_mux_array port 0")
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a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(a)
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debug.info(1, "Testing sample for 2-way column_mux_array port 1")
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a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
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self.local_check(a)
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debug.info(1, "Testing sample for 4-way column_mux_array port 0")
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a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(a)
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@@ -33,6 +41,14 @@ class single_level_column_mux_test(openram_test):
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a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
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self.local_check(a)
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debug.info(1, "Testing sample for 8-way column_mux_array port 0")
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a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(a)
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debug.info(1, "Testing sample for 8-way column_mux_array port 1")
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a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
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self.local_check(a)
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globals.end_openram()
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@@ -7,7 +7,7 @@
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# All rights reserved.
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#
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from testutils import *
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import sys,os
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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