From a862cf3cb21deff9c097f2d7bc51130906ee03e6 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Jun 2020 10:17:54 -0700 Subject: [PATCH] Test more single level col mux configs --- ...ingle_level_column_mux_array_1rw_1r_test.py | 18 +++++++++++++++++- .../07_single_level_column_mux_array_test.py | 2 +- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py index c758e788..209133aa 100755 --- a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py +++ b/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py @@ -7,7 +7,7 @@ # All rights reserved. # from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -25,6 +25,14 @@ class single_level_column_mux_test(openram_test): OPTS.num_w_ports = 0 globals.setup_bitcell() + debug.info(1, "Testing sample for 2-way column_mux_array port 0") + a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 2-way column_mux_array port 1") + a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + debug.info(1, "Testing sample for 4-way column_mux_array port 0") a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) @@ -33,6 +41,14 @@ class single_level_column_mux_test(openram_test): a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) + debug.info(1, "Testing sample for 8-way column_mux_array port 0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array port 1") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index b1f74eba..c0476a4f 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -7,7 +7,7 @@ # All rights reserved. # from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS