Port type order generated on the fly

2026-09-05 01:01:33 +02:00 · 2020-11-13 16:41:02 -08:00
parent 01d191da40
commit a2b17a271c
4 changed files with 7 additions and 10 deletions
@@ -23,7 +23,7 @@ class bitcell_base(design.design):

        if prop:
            self.pins = prop.port_names()
-            self.add_pin_types(prop.port_types)
+            self.add_pin_types(prop.port_types())
            self.nets_match = self.do_nets_exist(prop.storage_nets)
            self.mirror = prop.mirror
            self.end_caps = prop.end_caps