Port type order generated on the fly

2026-09-07 03:20:39 +02:00 · 2020-11-13 16:41:02 -08:00
parent 01d191da40
commit a2b17a271c
4 changed files with 7 additions and 10 deletions
@@ -39,7 +39,7 @@ class design(hierarchy_design):
                # The pins get added from the spice file
                debug.check(prop.port_names() == self.pins,
                            "Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names(), self.pins))
-                self.add_pin_types(prop.port_types)
+                self.add_pin_types(prop.port_types())
            
                (width, height) = utils.get_libcell_size(self.cell_name,
                                                         GDS["unit"],