From 8eb6caa248f6b6e2331724d9f4969afba06cc6dd Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 14 Dec 2021 22:15:27 -0800 Subject: [PATCH 1/7] fix bitcell array opc errors --- technology/sky130/modules/sky130_bitcell_array.py | 13 ++++++++++--- technology/sky130/modules/sky130_dummy_array.py | 14 ++++++++++---- technology/sky130/modules/sky130_internal.py | 2 ++ technology/sky130/modules/sky130_replica_column.py | 6 ++++-- 4 files changed, 26 insertions(+), 9 deletions(-) diff --git a/technology/sky130/modules/sky130_bitcell_array.py b/technology/sky130/modules/sky130_bitcell_array.py index 5d250f15..c71b6aa1 100644 --- a/technology/sky130/modules/sky130_bitcell_array.py +++ b/technology/sky130/modules/sky130_bitcell_array.py @@ -47,6 +47,8 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): self.add_mod(self.strap2) self.strap3 = factory.create(module_type="internal", version="wlstrapa") self.add_mod(self.strap3) + self.strap4 = factory.create(module_type="internal", version="wlstrapa_p") + self.add_mod(self.strap4) def create_instances(self): """ Create the module instances used in this design """ @@ -71,9 +73,14 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): self.connect_inst(self.get_bitcell_pins(row, col)) if col != self.column_size - 1: if alternate_strap: - row_layout.append(self.strap2) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), - mod=self.strap2) + if row % 2: + row_layout.append(self.strap4) + self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + mod=self.strap4) + else: + row_layout.append(self.strap2) + self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + mod=self.strap2) alternate_strap = 0 else: if row % 2: diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index 9f854dd8..063d5a79 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -52,6 +52,8 @@ class sky130_dummy_array(sky130_bitcell_base_array): self.add_mod(self.strap) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") self.add_mod(self.strap2) + self.strap3 = factory.create(module_type="internal", version="wlstrapa") + self.add_mod(self.strap3) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") def create_instances(self): @@ -82,10 +84,14 @@ class sky130_dummy_array(sky130_bitcell_base_array): mod=self.strap2) alternate_strap = 0 else: - - row_layout.append(self.strap) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), - mod=self.strap) + if col % 2: + row_layout.append(self.strap) + self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + mod=self.strap) + else: + row_layout.append(self.strap3) + self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + mod=self.strap3) alternate_strap = 1 self.connect_inst(self.get_strap_pins(row, col)) if alternate_bitcell == 0: diff --git a/technology/sky130/modules/sky130_internal.py b/technology/sky130/modules/sky130_internal.py index c481195f..b8c0616f 100644 --- a/technology/sky130/modules/sky130_internal.py +++ b/technology/sky130/modules/sky130_internal.py @@ -22,6 +22,8 @@ class sky130_internal(design.design): self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p" elif version == "wlstrapa": self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa" + elif version == "wlstrapa_p": + self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p" else: debug.error("Invalid version", -1) design.design.__init__(self, name=self.name) diff --git a/technology/sky130/modules/sky130_replica_column.py b/technology/sky130/modules/sky130_replica_column.py index a900b0fe..7169ae6a 100644 --- a/technology/sky130/modules/sky130_replica_column.py +++ b/technology/sky130/modules/sky130_replica_column.py @@ -104,6 +104,8 @@ class sky130_replica_column(sky130_bitcell_base_array): self.add_mod(self.strap1) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") self.add_mod(self.strap2) + self.strap3 = factory.create(module_type="internal", version="wlstrapa_p") + self.add_mod(self.strap3) self.colend = factory.create(module_type="col_cap", version="colend") self.edge_cell = self.colend @@ -140,8 +142,8 @@ class sky130_replica_column(sky130_bitcell_base_array): row_layout.append(self.replica_cell2) self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2) self.connect_inst(self.get_bitcell_pins(row, 0)) - row_layout.append(self.strap2) - self.add_inst(name=name + "_strap", mod=self.strap2) + row_layout.append(self.strap3) + self.add_inst(name=name + "_strap", mod=self.strap3) self.connect_inst(self.get_strap_pins(row, 0)) alternate_bitcell = 0 From ddb76c4affd3b5325579e06df20397a33f1750cf Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 15 Dec 2021 01:28:30 -0800 Subject: [PATCH 2/7] fix dummy array opc --- technology/sky130/modules/sky130_dummy_array.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index 063d5a79..e1cb3dfd 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -54,6 +54,8 @@ class sky130_dummy_array(sky130_bitcell_base_array): self.add_mod(self.strap2) self.strap3 = factory.create(module_type="internal", version="wlstrapa") self.add_mod(self.strap3) + self.strap4 = factory.create(module_type="internal", version="wlstrapa_p") + self.add_mod(self.strap4) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") def create_instances(self): @@ -79,9 +81,14 @@ class sky130_dummy_array(sky130_bitcell_base_array): self.connect_inst(self.get_bitcell_pins(row, col)) if col != self.column_size - 1: if alternate_strap: - row_layout.append(self.strap2) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), - mod=self.strap2) + if col % 2: + row_layout.append(self.strap4) + self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + mod=self.strap4) + else: + row_layout.append(self.strap4) + self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + mod=self.strap4) alternate_strap = 0 else: if col % 2: From 4e5744df507998fe9b81eae07472cd55dcbbbab1 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 15 Dec 2021 01:36:56 -0800 Subject: [PATCH 3/7] remove add_mod() --- technology/sky130/modules/sky130_bitcell_array.py | 6 ------ technology/sky130/modules/sky130_col_cap_array.py | 6 ------ technology/sky130/modules/sky130_dummy_array.py | 6 ------ technology/sky130/modules/sky130_replica_column.py | 9 --------- technology/sky130/modules/sky130_row_cap_array.py | 8 -------- 5 files changed, 35 deletions(-) diff --git a/technology/sky130/modules/sky130_bitcell_array.py b/technology/sky130/modules/sky130_bitcell_array.py index c71b6aa1..648f22d6 100644 --- a/technology/sky130/modules/sky130_bitcell_array.py +++ b/technology/sky130/modules/sky130_bitcell_array.py @@ -38,17 +38,11 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): """ Add the modules used in this design """ # Bitcell for port names only self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") - self.add_mod(self.cell) self.cell2 = factory.create(module_type=OPTS.bitcell, version="opt1a") - self.add_mod(self.cell2) self.strap = factory.create(module_type="internal", version="wlstrap") - self.add_mod(self.strap) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.add_mod(self.strap2) self.strap3 = factory.create(module_type="internal", version="wlstrapa") - self.add_mod(self.strap3) self.strap4 = factory.create(module_type="internal", version="wlstrapa_p") - self.add_mod(self.strap4) def create_instances(self): """ Create the module instances used in this design """ diff --git a/technology/sky130/modules/sky130_col_cap_array.py b/technology/sky130/modules/sky130_col_cap_array.py index b1e9e35b..26d97ee2 100644 --- a/technology/sky130/modules/sky130_col_cap_array.py +++ b/technology/sky130/modules/sky130_col_cap_array.py @@ -49,18 +49,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array): """ Add the modules used in this design """ if self.location == "top": self.colend1 = factory.create(module_type="col_cap", version="colend") - self.add_mod(self.colend1) self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent") - self.add_mod(self.colend2) self.colend3 = factory.create(module_type="col_cap", version="colend_cent") - self.add_mod(self.colend3) elif self.location == "bottom": self.colend1 = factory.create(module_type="col_cap", version="colenda") - self.add_mod(self.colend1) self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent") - self.add_mod(self.colend2) self.colend3 = factory.create(module_type="col_cap", version="colenda_cent") - self.add_mod(self.colend3) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index e1cb3dfd..c53b0fc3 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -45,17 +45,11 @@ class sky130_dummy_array(sky130_bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1") - self.add_mod(self.dummy_cell) self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a") - self.add_mod(self.dummy_cell2) self.strap = factory.create(module_type="internal", version="wlstrap") - self.add_mod(self.strap) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.add_mod(self.strap2) self.strap3 = factory.create(module_type="internal", version="wlstrapa") - self.add_mod(self.strap3) self.strap4 = factory.create(module_type="internal", version="wlstrapa_p") - self.add_mod(self.strap4) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") def create_instances(self): diff --git a/technology/sky130/modules/sky130_replica_column.py b/technology/sky130/modules/sky130_replica_column.py index 7169ae6a..f5dddf5d 100644 --- a/technology/sky130/modules/sky130_replica_column.py +++ b/technology/sky130/modules/sky130_replica_column.py @@ -92,30 +92,21 @@ class sky130_replica_column(sky130_bitcell_base_array): def add_modules(self): self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1") - self.add_mod(self.replica_cell) self.cell = self.replica_cell self.replica_cell2 = factory.create(module_type="replica_bitcell_1port", version="opt1a") - self.add_mod(self.replica_cell2) self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1") self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1") self.strap1 = factory.create(module_type="internal", version="wlstrap") - self.add_mod(self.strap1) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.add_mod(self.strap2) self.strap3 = factory.create(module_type="internal", version="wlstrapa_p") - self.add_mod(self.strap3) self.colend = factory.create(module_type="col_cap", version="colend") self.edge_cell = self.colend - self.add_mod(self.colend) self.colenda = factory.create(module_type="col_cap", version="colenda") - self.add_mod(self.colenda) self.colend_p_cent = factory.create(module_type="col_cap", version="colend_p_cent") - self.add_mod(self.colend_p_cent) self.colenda_p_cent = factory.create(module_type="col_cap", version="colenda_p_cent") - self.add_mod(self.colenda_p_cent) def create_instances(self): self.cell_inst = {} diff --git a/technology/sky130/modules/sky130_row_cap_array.py b/technology/sky130/modules/sky130_row_cap_array.py index a82f5558..e5721da2 100644 --- a/technology/sky130/modules/sky130_row_cap_array.py +++ b/technology/sky130/modules/sky130_row_cap_array.py @@ -51,24 +51,16 @@ class sky130_row_cap_array(sky130_bitcell_base_array): """ Add the modules used in this design """ if self.column_offset == 0: self.top_corner = factory.create(module_type="corner", location="ul") - self.add_mod(self.top_corner) self.bottom_corner =factory.create(module_type="corner", location="ll") - self.add_mod(self.bottom_corner) self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica") - self.add_mod(self.rowend1) self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica") - self.add_mod(self.rowend2) else: self.top_corner = factory.create(module_type="corner", location="ur") - self.add_mod(self.top_corner) self.bottom_corner = factory.create(module_type="corner", location="lr") - self.add_mod(self.bottom_corner) self.rowend1 = factory.create(module_type="row_cap", version="rowend") - self.add_mod(self.rowend1) self.rowend2 = factory.create(module_type="row_cap", version="rowenda") - self.add_mod(self.rowend2) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") From 8879820af4a59ef947d8a4cf46b3d43fbbe7161e Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 15 Dec 2021 14:19:52 -0800 Subject: [PATCH 4/7] replica col lvs fix --- compiler/modules/bitcell_base_array.py | 4 +- .../sky130/modules/sky130_bitcell_array.py | 11 ++- .../modules/sky130_bitcell_base_array.py | 19 +++-- .../sky130/modules/sky130_dummy_array.py | 15 ++-- .../modules/sky130_replica_bitcell_array.py | 80 +++++++++++++++++++ .../sky130/modules/sky130_replica_column.py | 20 ++--- technology/sky130/tech/tech.py | 2 +- 7 files changed, 119 insertions(+), 32 deletions(-) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index f9eeaeb7..5bff2448 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -43,11 +43,11 @@ class bitcell_base_array(design.design): # Make a flat list too self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl] - def create_all_wordline_names(self, row_size=None): + def create_all_wordline_names(self, row_size=None, start_row=0): if row_size == None: row_size = self.row_size - for row in range(row_size): + for row in range(start_row, row_size): for port in self.all_ports: self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) diff --git a/technology/sky130/modules/sky130_bitcell_array.py b/technology/sky130/modules/sky130_bitcell_array.py index 5d250f15..bd3a9457 100644 --- a/technology/sky130/modules/sky130_bitcell_array.py +++ b/technology/sky130/modules/sky130_bitcell_array.py @@ -71,21 +71,24 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): self.connect_inst(self.get_bitcell_pins(row, col)) if col != self.column_size - 1: if alternate_strap: + name="row_{}_col_{}_wlstrap_p".format(row, col) row_layout.append(self.strap2) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + self.add_inst(name=name.format(row, col), mod=self.strap2) alternate_strap = 0 else: if row % 2: + name="row_{}_col_{}_wlstrapa".format(row, col) row_layout.append(self.strap3) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + self.add_inst(name=name.format(row, col), mod=self.strap3) else: + name="row_{}_col_{}_wlstrap".format(row, col) row_layout.append(self.strap) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + self.add_inst(name=name.format(row, col), mod=self.strap) alternate_strap = 1 - self.connect_inst(self.get_strap_pins(row, col)) + self.connect_inst(self.get_strap_pins(row, col, name)) if alternate_bitcell == 0: alternate_bitcell = 1 else: diff --git a/technology/sky130/modules/sky130_bitcell_base_array.py b/technology/sky130/modules/sky130_bitcell_base_array.py index 5b0e39d4..b52d5eb9 100644 --- a/technology/sky130/modules/sky130_bitcell_base_array.py +++ b/technology/sky130/modules/sky130_bitcell_base_array.py @@ -77,21 +77,24 @@ class sky130_bitcell_base_array(bitcell_base_array): return bitcell_pins - def get_strap_pins(self, row, col): + def get_strap_pins(self, row, col, name=""): """ Creates a list of connections in the strap cell, indexed by column and row, for instance use in bitcell_array """ - strap_pins = ["vdd"] - return strap_pins - - def get_col_cap_pins(self, row, col): - """ - """ - strap_pins = ["gnd", "gnd", "vdd"] + if name and "_p" in name: + strap_pins = ["gnd"] + else: + strap_pins = ["vdd"] return strap_pins def get_col_cap_p_pins(self, row, col): + """ + """ + strap_pins = ["gnd", "vdd", "gnd"] + return strap_pins + + def get_col_cap_pins(self, row, col): """ """ strap_pins = [] diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index 9f854dd8..56f53d8b 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -77,17 +77,18 @@ class sky130_dummy_array(sky130_bitcell_base_array): self.connect_inst(self.get_bitcell_pins(row, col)) if col != self.column_size - 1: if alternate_strap: + name = "row_{}_col_{}_wlstrap_p".format(row, col) row_layout.append(self.strap2) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + self.add_inst(name=name, mod=self.strap2) alternate_strap = 0 else: - + name="row_{}_col_{}_wlstrap".format(row, col) row_layout.append(self.strap) - self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), + self.add_inst(name=name, mod=self.strap) alternate_strap = 1 - self.connect_inst(self.get_strap_pins(row, col)) + self.connect_inst(self.get_strap_pins(row, col, name)) if alternate_bitcell == 0: alternate_bitcell = 1 else: @@ -96,11 +97,11 @@ class sky130_dummy_array(sky130_bitcell_base_array): def add_pins(self): # bitline pins are not added because they are floating + for bl_name in self.get_bitline_names(): + self.add_pin(bl_name, "INOUT") for wl_name in self.get_wordline_names(): self.add_pin(wl_name, "INPUT") - for bl in range(self.column_size): - self.add_pin("dummy_bl_{}".format(bl)) - self.add_pin("dummy_br_{}".format(bl)) + self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") diff --git a/technology/sky130/modules/sky130_replica_bitcell_array.py b/technology/sky130/modules/sky130_replica_bitcell_array.py index bc5d2036..28312c6c 100644 --- a/technology/sky130/modules/sky130_replica_bitcell_array.py +++ b/technology/sky130/modules/sky130_replica_bitcell_array.py @@ -338,3 +338,83 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar width=pin.width(), height=self.height - 2 *(pin_height + drc_width*2)) return + + def add_wordline_pins(self): + + # Wordlines to ground + self.gnd_wordline_names = [] + + for port in self.all_ports: + for bit in self.all_ports: + self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit)) + if bit != port: + self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit)) + + self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl] + + self.wordline_names = self.bitcell_array.wordline_names + self.all_wordline_names = self.bitcell_array.all_wordline_names + + # All wordlines including dummy and RBL + self.replica_array_wordline_names = [] + #self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names())) + for bit in range(self.rbl[0]): + self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]]) + self.replica_array_wordline_names.extend(self.all_wordline_names) + for bit in range(self.rbl[1]): + self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]]) + #self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names())) + + for port in range(self.rbl[0]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") + self.add_pin_list(self.all_wordline_names, "INPUT") + for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") + + def create_instances(self): + """ Create the module instances used in this design """ + self.supplies = ["vdd", "gnd"] + + # Used for names/dimensions only + # self.cell = factory.create(module_type=OPTS.bitcell) + + # Main array + self.bitcell_array_inst=self.add_inst(name="bitcell_array", + mod=self.bitcell_array) + self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies) + print("running\n\n\n") + # Replica columns + self.replica_col_insts = [] + for port in self.all_ports: + if port in self.rbls: + self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), + mod=self.replica_columns[port])) + self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies) + else: + self.replica_col_insts.append(None) + + # Dummy rows under the bitcell array (connected with with the replica cell wl) + self.dummy_row_replica_insts = [] + # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! + for port in self.all_ports: + self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), + mod=self.dummy_row)) + self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies) + + # Top/bottom dummy rows or col caps + self.dummy_row_insts = [] + self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", + mod=self.col_cap_bottom)) + self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies) + self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", + mod=self.col_cap_top)) + self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies) + + # Left/right Dummy columns + self.dummy_col_insts = [] + self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", + mod=self.row_cap_left)) + self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.replica_array_wordline_names + self.supplies) + self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", + mod=self.row_cap_right)) + self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.replica_array_wordline_names + self.supplies) diff --git a/technology/sky130/modules/sky130_replica_column.py b/technology/sky130/modules/sky130_replica_column.py index a900b0fe..db37d26f 100644 --- a/technology/sky130/modules/sky130_replica_column.py +++ b/technology/sky130/modules/sky130_replica_column.py @@ -81,9 +81,9 @@ class sky130_replica_column(sky130_bitcell_base_array): def add_pins(self): self.create_all_bitline_names() - self.create_all_wordline_names(self.row_size+2) + #self.create_all_wordline_names(self.row_size+2) # +2 to add fake wl pins for colends - + self.create_all_wordline_names(self.row_size+1, 1) self.add_pin_list(self.all_bitline_names, "OUTPUT") self.add_pin_list(self.all_wordline_names, "INPUT") @@ -132,8 +132,8 @@ class sky130_replica_column(sky130_bitcell_base_array): self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell) self.connect_inst(self.get_bitcell_pins(row, 0)) row_layout.append(self.strap2) - self.add_inst(name=name + "_strap", mod=self.strap2) - self.connect_inst(self.get_strap_pins(row, 0)) + self.add_inst(name=name + "_strap_p", mod=self.strap2) + self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p")) alternate_bitcell = 1 else: @@ -141,24 +141,24 @@ class sky130_replica_column(sky130_bitcell_base_array): self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2) self.connect_inst(self.get_bitcell_pins(row, 0)) row_layout.append(self.strap2) - self.add_inst(name=name + "_strap", mod=self.strap2) - self.connect_inst(self.get_strap_pins(row, 0)) + self.add_inst(name=name + "_strap_p", mod=self.strap2) + self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p")) alternate_bitcell = 0 elif (row == 0): row_layout.append(self.colend) self.cell_inst[row]=self.add_inst(name=name, mod=self.colend) - self.connect_inst(self.get_col_cap_p_pins(row, 0)) + self.connect_inst(self.get_col_cap_pins(row, 0)) row_layout.append(self.colend_p_cent) self.add_inst(name=name + "_cap", mod=self.colend_p_cent) - self.connect_inst(self.get_col_cap_pins(row, 0)) + self.connect_inst(self.get_col_cap_p_pins(row, 0)) elif (row == self.total_size - 1): row_layout.append(self.colenda) self.cell_inst[row]=self.add_inst(name=name, mod=self.colenda) - self.connect_inst(self.get_col_cap_p_pins(row, 0)) + self.connect_inst(self.get_col_cap_pins(row, 0)) row_layout.append(self.colenda_p_cent) self.add_inst(name=name + "_cap", mod=self.colenda_p_cent) - self.connect_inst(self.get_col_cap_pins(row, 0)) + self.connect_inst(self.get_col_cap_p_pins(row, 0)) self.array_layout.append(row_layout) diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py index a2c4d185..f82855c6 100644 --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -100,7 +100,7 @@ cell_properties.bitcell_2port.port_map = {'bl0': 'BL0', 'gnd': 'GND'} cell_properties.col_cap_1port_bitcell = cell(['br', 'vdd', 'gnd', 'bl'], - ['INPUT', 'INPUT', 'GROUND', 'POWER'], + ['INPUT', 'POWER', 'GROUND', 'INPUT'], {'bl': 'BL0', 'br': 'BL1', 'vdd': 'VPWR', From 8a0450afac5fa24a8d70868ffe3d32231f7ba908 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 22 Dec 2021 15:46:03 -0800 Subject: [PATCH 5/7] adjust replica col wls --- technology/sky130/modules/sky130_replica_bitcell_array.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/technology/sky130/modules/sky130_replica_bitcell_array.py b/technology/sky130/modules/sky130_replica_bitcell_array.py index 28312c6c..0e7469de 100644 --- a/technology/sky130/modules/sky130_replica_bitcell_array.py +++ b/technology/sky130/modules/sky130_replica_bitcell_array.py @@ -382,7 +382,6 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar self.bitcell_array_inst=self.add_inst(name="bitcell_array", mod=self.bitcell_array) self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies) - print("running\n\n\n") # Replica columns self.replica_col_insts = [] for port in self.all_ports: @@ -414,7 +413,7 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar self.dummy_col_insts = [] self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", mod=self.row_cap_left)) - self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.replica_array_wordline_names + self.supplies) + self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + ["gnd"] + self.replica_array_wordline_names + ["gnd"] + self.supplies) self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", mod=self.row_cap_right)) - self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.replica_array_wordline_names + self.supplies) + self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + ["gnd"] + self.replica_array_wordline_names + ["gnd"] + self.supplies) From 468de963f678874d9265aefbe7c6af6cbae1de3b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 22 Dec 2021 15:51:49 -0800 Subject: [PATCH 6/7] remove add_mod in sky130 --- technology/sky130/modules/sky130_bitcell_array.py | 5 ----- technology/sky130/modules/sky130_col_cap_array.py | 6 ------ technology/sky130/modules/sky130_dummy_array.py | 4 ---- technology/sky130/modules/sky130_replica_column.py | 8 -------- technology/sky130/modules/sky130_row_cap_array.py | 8 -------- 5 files changed, 31 deletions(-) diff --git a/technology/sky130/modules/sky130_bitcell_array.py b/technology/sky130/modules/sky130_bitcell_array.py index bd3a9457..32fd5e4b 100644 --- a/technology/sky130/modules/sky130_bitcell_array.py +++ b/technology/sky130/modules/sky130_bitcell_array.py @@ -38,15 +38,10 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): """ Add the modules used in this design """ # Bitcell for port names only self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") - self.add_mod(self.cell) self.cell2 = factory.create(module_type=OPTS.bitcell, version="opt1a") - self.add_mod(self.cell2) self.strap = factory.create(module_type="internal", version="wlstrap") - self.add_mod(self.strap) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.add_mod(self.strap2) self.strap3 = factory.create(module_type="internal", version="wlstrapa") - self.add_mod(self.strap3) def create_instances(self): """ Create the module instances used in this design """ diff --git a/technology/sky130/modules/sky130_col_cap_array.py b/technology/sky130/modules/sky130_col_cap_array.py index b1e9e35b..26d97ee2 100644 --- a/technology/sky130/modules/sky130_col_cap_array.py +++ b/technology/sky130/modules/sky130_col_cap_array.py @@ -49,18 +49,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array): """ Add the modules used in this design """ if self.location == "top": self.colend1 = factory.create(module_type="col_cap", version="colend") - self.add_mod(self.colend1) self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent") - self.add_mod(self.colend2) self.colend3 = factory.create(module_type="col_cap", version="colend_cent") - self.add_mod(self.colend3) elif self.location == "bottom": self.colend1 = factory.create(module_type="col_cap", version="colenda") - self.add_mod(self.colend1) self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent") - self.add_mod(self.colend2) self.colend3 = factory.create(module_type="col_cap", version="colenda_cent") - self.add_mod(self.colend3) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index 56f53d8b..66116417 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -45,13 +45,9 @@ class sky130_dummy_array(sky130_bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1") - self.add_mod(self.dummy_cell) self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a") - self.add_mod(self.dummy_cell2) self.strap = factory.create(module_type="internal", version="wlstrap") - self.add_mod(self.strap) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.add_mod(self.strap2) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") def create_instances(self): diff --git a/technology/sky130/modules/sky130_replica_column.py b/technology/sky130/modules/sky130_replica_column.py index db37d26f..482b22e2 100644 --- a/technology/sky130/modules/sky130_replica_column.py +++ b/technology/sky130/modules/sky130_replica_column.py @@ -92,28 +92,20 @@ class sky130_replica_column(sky130_bitcell_base_array): def add_modules(self): self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1") - self.add_mod(self.replica_cell) self.cell = self.replica_cell self.replica_cell2 = factory.create(module_type="replica_bitcell_1port", version="opt1a") - self.add_mod(self.replica_cell2) self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1") self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1") self.strap1 = factory.create(module_type="internal", version="wlstrap") - self.add_mod(self.strap1) self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.add_mod(self.strap2) self.colend = factory.create(module_type="col_cap", version="colend") self.edge_cell = self.colend - self.add_mod(self.colend) self.colenda = factory.create(module_type="col_cap", version="colenda") - self.add_mod(self.colenda) self.colend_p_cent = factory.create(module_type="col_cap", version="colend_p_cent") - self.add_mod(self.colend_p_cent) self.colenda_p_cent = factory.create(module_type="col_cap", version="colenda_p_cent") - self.add_mod(self.colenda_p_cent) def create_instances(self): self.cell_inst = {} diff --git a/technology/sky130/modules/sky130_row_cap_array.py b/technology/sky130/modules/sky130_row_cap_array.py index a82f5558..e5721da2 100644 --- a/technology/sky130/modules/sky130_row_cap_array.py +++ b/technology/sky130/modules/sky130_row_cap_array.py @@ -51,24 +51,16 @@ class sky130_row_cap_array(sky130_bitcell_base_array): """ Add the modules used in this design """ if self.column_offset == 0: self.top_corner = factory.create(module_type="corner", location="ul") - self.add_mod(self.top_corner) self.bottom_corner =factory.create(module_type="corner", location="ll") - self.add_mod(self.bottom_corner) self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica") - self.add_mod(self.rowend1) self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica") - self.add_mod(self.rowend2) else: self.top_corner = factory.create(module_type="corner", location="ur") - self.add_mod(self.top_corner) self.bottom_corner = factory.create(module_type="corner", location="lr") - self.add_mod(self.bottom_corner) self.rowend1 = factory.create(module_type="row_cap", version="rowend") - self.add_mod(self.rowend1) self.rowend2 = factory.create(module_type="row_cap", version="rowenda") - self.add_mod(self.rowend2) self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") From cf8c486cea4513faf181ecf28626b544b4393d30 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 22 Dec 2021 16:00:59 -0800 Subject: [PATCH 7/7] merge sky130_dummy_array --- technology/sky130/modules/sky130_dummy_array.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/modules/sky130_dummy_array.py index f1097855..c53b0fc3 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/modules/sky130_dummy_array.py @@ -94,7 +94,7 @@ class sky130_dummy_array(sky130_bitcell_base_array): self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col), mod=self.strap3) alternate_strap = 1 - self.connect_inst(self.get_strap_pins(row, col, name)) + self.connect_inst(self.get_strap_pins(row, col)) if alternate_bitcell == 0: alternate_bitcell = 1 else: @@ -103,11 +103,11 @@ class sky130_dummy_array(sky130_bitcell_base_array): def add_pins(self): # bitline pins are not added because they are floating - for bl_name in self.get_bitline_names(): - self.add_pin(bl_name, "INOUT") for wl_name in self.get_wordline_names(): self.add_pin(wl_name, "INPUT") - + for bl in range(self.column_size): + self.add_pin("dummy_bl_{}".format(bl)) + self.add_pin("dummy_br_{}".format(bl)) self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND")