From 92fc30005c028db65376e784c57df1fb5d8043eb Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Jun 2020 16:55:49 -0700 Subject: [PATCH] Use factory in and_dec tests --- compiler/tests/04_and2_dec_test.py | 11 +++++++---- compiler/tests/04_and3_dec_test.py | 11 +++++++---- compiler/tests/04_and4_dec_test.py | 13 ++++++++----- 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py index 355d3b15..97ac5749 100755 --- a/compiler/tests/04_and2_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -23,10 +23,13 @@ class and2_dec_test(openram_test): global verify import verify - import and2_dec - - debug.info(2, "Testing and2 gate 4x") - a = and2_dec.and2_dec(name="and2x4", size=4) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and2_dec gate") + a = factory.create(module_type="and2_dec") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py index 7794f36b..ec83335b 100755 --- a/compiler/tests/04_and3_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -23,10 +23,13 @@ class and3_dec_test(openram_test): global verify import verify - import and3_dec - - debug.info(2, "Testing and3 gate 4x") - a = and3_dec.and3_dec(name="and3x4", size=4) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and3_dec gate") + a = factory.create(module_type="and3_dec") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index 7794f36b..bdd91c40 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class and3_dec_test(openram_test): +class and4_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -23,10 +23,13 @@ class and3_dec_test(openram_test): global verify import verify - import and3_dec - - debug.info(2, "Testing and3 gate 4x") - a = and3_dec.and3_dec(name="and3x4", size=4) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and4_dec gate") + a = factory.create(module_type="and4_dec") self.local_check(a) globals.end_openram()