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modules: Use add_power_pin API for all modules 

sense_amp_array, write_driver_array, and single_column_mux were the only offenders.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-12-23 16:37:16 +01:00
parent 988df8ebb9
commit 90a4a72bba
3 changed files with 17 additions and 27 deletions
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21
compiler/modules/sense_amp_array.py
View File

@ -98,18 +98,15 @@ class sense_amp_array(design.design):
for i in range(len(self.local_insts)): for i in range(len(self.local_insts)):
inst = self.local_insts[i] inst = self.local_insts[i]
gnd_pos = inst.get_pin("gnd").center() self.add_power_pin(name = "gnd",
self.add_via_center(layers=self.m2_stack, loc = inst.get_pin("gnd").center(),
offset=gnd_pos) start_layer="m2",
self.add_layout_pin_rect_center(text="gnd", vertical=True)
layer="m3",
offset=gnd_pos) self.add_power_pin(name = "vdd",
vdd_pos = inst.get_pin("vdd").center() loc = inst.get_pin("vdd").center(),
self.add_via_center(layers=self.m2_stack, start_layer="m2",
offset=vdd_pos) vertical=True)
self.add_layout_pin_rect_center(text="vdd",
layer="m3",
offset=vdd_pos)
bl_pin = inst.get_pin("bl") bl_pin = inst.get_pin("bl")
br_pin = inst.get_pin("br") br_pin = inst.get_pin("br")

11
compiler/modules/write_driver_array.py
View File

@ -141,13 +141,10 @@ class write_driver_array(design.design):
for n in ["vdd", "gnd"]: for n in ["vdd", "gnd"]:
pin_list = self.driver_insts[i].get_pins(n) pin_list = self.driver_insts[i].get_pins(n)
for pin in pin_list: for pin in pin_list:
pin_pos = pin.center() self.add_power_pin(name = n,
# Add the M2->M3 stack loc = pin.center(),
self.add_via_center(layers=self.m2_stack, vertical=True,
offset=pin_pos) start_layer = "m2")
self.add_layout_pin_rect_center(text=n,
layer="m3",
offset=pin_pos)
if self.write_size: if self.write_size:
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
en_pin = self.driver_insts[bit*self.write_size].get_pin("en") en_pin = self.driver_insts[bit*self.write_size].get_pin("en")

12
compiler/pgates/single_level_column_mux.py
View File

@ -180,14 +180,10 @@ class single_level_column_mux(pgate.pgate):
implant_type="p", implant_type="p",
well_type="p") well_type="p")
# Add the M1->M2->M3 stack # Add the M1->..->power_grid_layer stack
self.add_via_center(layers=self.m1_stack, self.add_power_pin(name = "gnd",
offset=active_pos) loc = active_pos,
self.add_via_center(layers=self.m2_stack, start_layer="m1")
offset=active_pos)
self.add_layout_pin_rect_center(text="gnd",
layer="m3",
offset=active_pos)
# Add well enclosure over all the tx and contact # Add well enclosure over all the tx and contact
self.add_rect(layer="pwell", self.add_rect(layer="pwell",