diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 2447e4b8..ca5afc47 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -98,18 +98,15 @@ class sense_amp_array(design.design):
         for i in range(len(self.local_insts)):
             inst = self.local_insts[i]
             
-            gnd_pos = inst.get_pin("gnd").center()
-            self.add_via_center(layers=self.m2_stack,
-                                offset=gnd_pos)
-            self.add_layout_pin_rect_center(text="gnd",
-                                            layer="m3",
-                                            offset=gnd_pos)
-            vdd_pos = inst.get_pin("vdd").center()
-            self.add_via_center(layers=self.m2_stack,
-                                offset=vdd_pos)
-            self.add_layout_pin_rect_center(text="vdd",
-                                            layer="m3",
-                                            offset=vdd_pos)
+            self.add_power_pin(name = "gnd",
+                               loc = inst.get_pin("gnd").center(),
+                               start_layer="m2",
+                               vertical=True)
+
+            self.add_power_pin(name = "vdd",
+                               loc = inst.get_pin("vdd").center(),
+                               start_layer="m2",
+                               vertical=True)
 
             bl_pin = inst.get_pin("bl")            
             br_pin = inst.get_pin("br")
diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py
index ac4dab00..900a8294 100644
--- a/compiler/modules/write_driver_array.py
+++ b/compiler/modules/write_driver_array.py
@@ -141,13 +141,10 @@ class write_driver_array(design.design):
             for n in ["vdd", "gnd"]:
                 pin_list = self.driver_insts[i].get_pins(n)
                 for pin in pin_list:
-                    pin_pos = pin.center()
-                    # Add the M2->M3 stack 
-                    self.add_via_center(layers=self.m2_stack,
-                                        offset=pin_pos)
-                    self.add_layout_pin_rect_center(text=n,
-                                                    layer="m3",
-                                                    offset=pin_pos)
+                    self.add_power_pin(name = n,
+                                       loc = pin.center(),
+                                       vertical=True,
+                                       start_layer = "m2")
         if self.write_size:
             for bit in range(self.num_wmasks):
                 en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py
index 18b4b10f..66faf1da 100644
--- a/compiler/pgates/single_level_column_mux.py
+++ b/compiler/pgates/single_level_column_mux.py
@@ -180,14 +180,10 @@ class single_level_column_mux(pgate.pgate):
                             implant_type="p",
                             well_type="p")
 
-        # Add the M1->M2->M3 stack
-        self.add_via_center(layers=self.m1_stack,
-                            offset=active_pos)
-        self.add_via_center(layers=self.m2_stack,
-                            offset=active_pos)
-        self.add_layout_pin_rect_center(text="gnd",
-                                        layer="m3",
-                                        offset=active_pos)
+        # Add the M1->..->power_grid_layer stack
+        self.add_power_pin(name = "gnd",
+                           loc = active_pos,
+                           start_layer="m1")
 
         # Add well enclosure over all the tx and contact
         self.add_rect(layer="pwell",