mirror of https://github.com/VLSIDA/OpenRAM.git
Small fix for finding pin names in timing graph.
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86799ae3ff
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@ -91,7 +91,7 @@ class bitcell_2port(bitcell_base.bitcell_base):
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def build_graph(self, graph, inst_name, port_nets):
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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to use the add_graph_edges function."""
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to use the add_graph_edges function."""
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pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
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pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)}
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Port 0 edges
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# Port 0 edges
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graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
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graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
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@ -41,7 +41,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
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def build_graph(self, graph, inst_name, port_nets):
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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to use the add_graph_edges function."""
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to use the add_graph_edges function."""
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pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
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pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)}
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Port 0 edges
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# Port 0 edges
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graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
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graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
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@ -67,7 +67,7 @@ class sense_amp(design.design):
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"""Returns name used for enable net"""
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"""Returns name used for enable net"""
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# FIXME: A better programmatic solution to designate pins
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# FIXME: A better programmatic solution to designate pins
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enable_name = self.en_name
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enable_name = self.en_name
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debug.check(enable_name in self.pins, "Enable name {} not found in pin list".format(enable_name))
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debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
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return enable_name
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return enable_name
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def build_graph(self, graph, inst_name, port_nets):
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def build_graph(self, graph, inst_name, port_nets):
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