diff --git a/compiler/bitcells/bitcell_2port.py b/compiler/bitcells/bitcell_2port.py index 87db10be..6a9f0b6f 100644 --- a/compiler/bitcells/bitcell_2port.py +++ b/compiler/bitcells/bitcell_2port.py @@ -91,7 +91,7 @@ class bitcell_2port(bitcell_base.bitcell_base): def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} + pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)} # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self) diff --git a/compiler/bitcells/replica_bitcell_2port.py b/compiler/bitcells/replica_bitcell_2port.py index 0709ca10..710a18d7 100644 --- a/compiler/bitcells/replica_bitcell_2port.py +++ b/compiler/bitcells/replica_bitcell_2port.py @@ -41,7 +41,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base): def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} + pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)} # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self) diff --git a/compiler/custom/sense_amp.py b/compiler/custom/sense_amp.py index 10156e2c..d57bdaac 100644 --- a/compiler/custom/sense_amp.py +++ b/compiler/custom/sense_amp.py @@ -67,7 +67,7 @@ class sense_amp(design.design): """Returns name used for enable net""" # FIXME: A better programmatic solution to designate pins enable_name = self.en_name - debug.check(enable_name in self.pins, "Enable name {} not found in pin list".format(enable_name)) + debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name)) return enable_name def build_graph(self, graph, inst_name, port_nets):