From 4a400b225de01334b920a4a3058fff695faccd9f Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 6 Jun 2022 15:40:00 -0700 Subject: [PATCH 1/2] update netgen in dockerfile --- docker/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 3922477c..21f15e9e 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -112,7 +112,7 @@ RUN rm -rf /root/ngspice ### Netgen ### #ARG NETGEN_COMMIT=1.5.219 -ARG NETGEN_COMMIT=88d53fab15eb611cffc024eebf8743fae5cf8cb7 +ARG NETGEN_COMMIT=89ef83c597d799be7777cdde7af6a6fb9f96bc29 WORKDIR /root #RUN git clone https://github.com/RTimothyEdwards/netgen.git netgen RUN git clone git://opencircuitdesign.com/netgen netgen From d8ae19c0cd00b44d497f60a69938f394772efd2e Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 6 Jun 2022 16:11:53 -0700 Subject: [PATCH 2/2] update single port macros --- .../sky130_sram_1kbyte_1rw_32x256_8.py | 2 ++ .../sky130_sram_2kbyte_1rw_32x512_8.py | 2 ++ .../sky130_sram_4kbyte_1rw_32x1024_8.py | 2 ++ .../sky130_sram_4kbyte_1rw_64x512_8.py | 21 +++++++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 macros/configs/sky130_sram_4kbyte_1rw_64x512_8.py diff --git a/macros/configs/sky130_sram_1kbyte_1rw_32x256_8.py b/macros/configs/sky130_sram_1kbyte_1rw_32x256_8.py index 955d3959..88bbfd6f 100644 --- a/macros/configs/sky130_sram_1kbyte_1rw_32x256_8.py +++ b/macros/configs/sky130_sram_1kbyte_1rw_32x256_8.py @@ -13,6 +13,8 @@ write_size = 8 # Bits num_rw_ports = 1 num_r_ports = 0 num_w_ports = 0 +num_spare_rows = 1 +num_spare_cols = 1 ports_human = '1rw' import os diff --git a/macros/configs/sky130_sram_2kbyte_1rw_32x512_8.py b/macros/configs/sky130_sram_2kbyte_1rw_32x512_8.py index 7f64d18c..8e2be639 100644 --- a/macros/configs/sky130_sram_2kbyte_1rw_32x512_8.py +++ b/macros/configs/sky130_sram_2kbyte_1rw_32x512_8.py @@ -13,6 +13,8 @@ write_size = 8 # Bits num_rw_ports = 1 num_r_ports = 0 num_w_ports = 0 +num_spare_rows = 1 +num_spare_cols = 1 ports_human = '1rw' import os diff --git a/macros/configs/sky130_sram_4kbyte_1rw_32x1024_8.py b/macros/configs/sky130_sram_4kbyte_1rw_32x1024_8.py index 571ca030..50c01e92 100644 --- a/macros/configs/sky130_sram_4kbyte_1rw_32x1024_8.py +++ b/macros/configs/sky130_sram_4kbyte_1rw_32x1024_8.py @@ -14,6 +14,8 @@ write_size = 8 # Bits num_rw_ports = 1 num_r_ports = 0 num_w_ports = 0 +num_spare_rows = 1 +num_spare_cols = 1 ports_human = '1rw' import os diff --git a/macros/configs/sky130_sram_4kbyte_1rw_64x512_8.py b/macros/configs/sky130_sram_4kbyte_1rw_64x512_8.py new file mode 100644 index 00000000..34ae8537 --- /dev/null +++ b/macros/configs/sky130_sram_4kbyte_1rw_64x512_8.py @@ -0,0 +1,21 @@ +""" +Single port, 1 kbytes SRAM, with byte write, useful for RISC-V processor main +memory. +""" +word_size = 64 # Bits +num_words = 512 +human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) + +# Allow byte writes +write_size = 8 # Bits + +# Single port +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 +num_spare_rows = 1 +num_spare_cols = 1 +ports_human = '1rw' + +import os +exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())