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Merge branch 'dev' into pdriver

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This commit is contained in:
Jennifer Eve Sowash
2018-12-06 14:38:08 -08:00
parent 5e19cf1e24 c51752d245
commit 8ea85e3e65
81 changed files with 1646 additions and 1891 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/11_dff_inv_test.py → compiler/tests/04_pand2_test.py
+9 -6
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@@ -1,6 +1,6 @@
#!/usr/bin/env python3
"""
Run a regression test on a dff_inv.
Run a regression test on a pand2 cell
"""
import unittest
@@ -11,19 +11,22 @@ import globals
from globals import OPTS
import debug
class dff_inv_test(openram_test):
class pand2_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_inv
global verify
import verify
debug.info(2, "Testing dff_inv 4x")
a = dff_inv.dff_inv(4)
import pand2
debug.info(2, "Testing pand2 gate 4x")
a = pand2.pand2(4)
self.local_check(a)
globals.end_openram()
# run the test from the command line
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
compiler/tests/04_pbuf_test.py
Regular → Executable
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compiler/tests/11_dff_inv_array_test.py
-39
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@@ -1,39 +0,0 @@
#!/usr/bin/env python3
"""
Run a regression test on a dff_array.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_inv_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_inv_array
debug.info(2, "Testing dff_inv_array for 3x3")
a = dff_inv_array.dff_inv_array(rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_inv_array for 1x3")
a = dff_inv_array.dff_inv_array(rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_inv_array for 3x1")
a = dff_inv_array.dff_inv_array(rows=3, columns=1)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/19_multi_bank_test.py
+4
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@@ -24,18 +24,21 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_multi")
self.local_check(a)
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_multi")
self.local_check(a)
c.num_words=64
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_multi")
self.local_check(a)
@@ -43,6 +46,7 @@ class multi_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_multi")
self.local_check(a)
compiler/tests/19_psingle_bank_test.py
+4
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@@ -31,6 +31,7 @@ class psingle_bank_test(openram_test):
num_words=16)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "No column mux")
name = "bank1_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
@@ -38,6 +39,7 @@ class psingle_bank_test(openram_test):
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two way column mux")
name = "bank2_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
@@ -45,6 +47,7 @@ class psingle_bank_test(openram_test):
c.num_words=64
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Four way column mux")
name = "bank3_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
@@ -53,6 +56,7 @@ class psingle_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Four way column mux")
name = "bank4_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
Executable
+51
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@@ -0,0 +1,51 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_1rw_1w_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 0
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
+10 -3
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@@ -11,8 +11,8 @@ import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_test(openram_test):
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
@@ -30,7 +30,14 @@ class psram_1bank_2mux_test(openram_test):
num_banks=1)
c.num_words=32
c.words_per_row=2
debug.info(1, "Single bank two way column mux 1w/1r with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_psram_1bank_2mux_test.py
+9 -2
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@@ -11,7 +11,7 @@ import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
class psram_1bank_2mux_test(openram_test):
def runTest(self):
@@ -31,7 +31,14 @@ class psram_1bank_2mux_test(openram_test):
num_banks=1)
c.num_words=32
c.words_per_row=2
debug.info(1, "Single bank two way column mux with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
Executable
+50
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@@ -0,0 +1,50 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class psram_1bank_4mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
c = sram_config(word_size=4,
num_words=64,
num_banks=1)
c.num_words=64
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
+8 -1
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@@ -29,7 +29,14 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
num_banks=1)
c.words_per_row=2
debug.info(1, "Single bank, two way column mux 1rw, 1r with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_1bank_2mux_test.py
+8 -1
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@@ -23,7 +23,14 @@ class sram_1bank_2mux_test(openram_test):
num_banks=1)
c.words_per_row=2
debug.info(1, "Single bank two way column mux with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_1bank_4mux_test.py
+8 -1
View File
@@ -23,7 +23,14 @@ class sram_1bank_4mux_test(openram_test):
num_banks=1)
c.words_per_row=4
debug.info(1, "Single bank, four way column mux with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
Executable
+50
View File
@@ -0,0 +1,50 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class sram_1bank_8mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
c = sram_config(word_size=2,
num_words=128,
num_banks=1)
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/20_sram_1bank_8mux_test.py
+8 -1
View File
@@ -23,7 +23,14 @@ class sram_1bank_8mux_test(openram_test):
num_banks=1)
c.words_per_row=8
debug.info(1, "Single bank, eight way column mux with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
+8 -1
View File
@@ -29,7 +29,14 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
num_banks=1)
c.words_per_row=1
debug.info(1, "Single bank, no column mux 1rw, 1r with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_1bank_nomux_test.py
+8 -1
View File
@@ -23,7 +23,14 @@ class sram_1bank_nomux_test(openram_test):
num_banks=1)
c.words_per_row=1
debug.info(1, "Single bank, no column mux with control logic")
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_2bank_test.py
+4
View File
@@ -23,18 +23,21 @@ class sram_2bank_test(openram_test):
num_banks=2)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Two bank, no column mux with control logic")
a = sram(c, "sram1")
self.local_check(a, final_verification=True)
c.num_words=64
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two bank two way column mux with control logic")
a = sram(c, "sram2")
self.local_check(a, final_verification=True)
c.num_words=128
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Two bank, four way column mux with control logic")
a = sram(c, "sram3")
self.local_check(a, final_verification=True)
@@ -42,6 +45,7 @@ class sram_2bank_test(openram_test):
c.word_size=2
c.num_words=256
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Two bank, eight way column mux with control logic")
a = sram(c, "sram4")
self.local_check(a, final_verification=True)
compiler/tests/20_sram_4bank_test.py
-55
View File
@@ -1,55 +0,0 @@
#!/usr/bin/env python3
"""
Run a regression test on a 4 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
@unittest.skip("Multibank is not working yet.")
class sram_4bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=16,
num_words=64,
num_banks=4)
debug.info(1, "Four bank, no column mux with control logic")
a = sram(c, "sram1")
self.local_check(a, final_verification=True)
c.num_words=128
c.words_per_row=2
debug.info(1, "Four bank two way column mux with control logic")
a = sram(c, "sram2")
self.local_check(a, final_verification=True)
c.num_words=256
c.words_per_row=4
debug.info(1, "Four bank, four way column mux with control logic")
a = sram(c, "sram3")
self.local_check(a, final_verification=True)
c.word_size=2
c.num_words=256
c.words_per_row=8
debug.info(1, "Four bank, eight way column mux with control logic")
a = sram.sram(c, "sram4")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/21_hspice_delay_test.py
+20 -20
View File
@@ -30,6 +30,7 @@ class timing_sram_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
@@ -49,29 +50,28 @@ class timing_sram_test(openram_test):
#Combine info about port into all data
data.update(port_data[0])
#Assumes single rw port (6t sram)
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [2.5829000000000004],
'delay_lh': [0.2255964],
'leakage_power': 0.0019498999999999996,
golden_data = {'delay_hl': [2.6232],
'delay_lh': [0.2775342],
'leakage_power': 0.0020258999999999997,
'min_period': 4.844,
'read0_power': [0.055371399999999994],
'read1_power': [0.0520225],
'slew_hl': [0.0794261],
'slew_lh': [0.0236264],
'write0_power': [0.06545659999999999],
'write1_power': [0.057846299999999996]}
'read0_power': [0.0557804],
'read1_power': [0.0525619],
'slew_hl': [0.1082014],
'slew_lh': [0.0238257],
'write0_power': [0.0456528],
'write1_power': [0.0442747]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.452],
'delay_lh': [1.3792000000000002],
'leakage_power': 0.0257065,
'min_period': 4.688,
'read0_power': [15.0755],
'read1_power': [14.4526],
'slew_hl': [0.6137363],
'slew_lh': [0.3381045],
'write0_power': [16.9203],
'write1_power': [15.367]}
golden_data = {'delay_hl': [6.079300000000001],
'delay_lh': [1.7767000000000002],
'leakage_power': 0.026282499999999997,
'min_period': 9.375,
'read0_power': [6.5802],
'read1_power': [6.2815],
'slew_hl': [0.7396921999999999],
'slew_lh': [0.3397355],
'write0_power': [5.7337],
'write1_power': [5.8691]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
compiler/tests/21_ngspice_delay_test.py
+20 -19
View File
@@ -30,6 +30,7 @@ class timing_sram_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
@@ -50,27 +51,27 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [2.584251],
'delay_lh': [0.22870469999999998],
'leakage_power': 0.0009567935,
golden_data = {'delay_hl': [2.625351],
'delay_lh': [0.28080869999999997],
'leakage_power': 0.001040682,
'min_period': 4.844,
'read0_power': [0.0547588],
'read1_power': [0.051159970000000006],
'slew_hl': [0.08164099999999999],
'slew_lh': [0.025474979999999998],
'write0_power': [0.06513271999999999],
'write1_power': [0.058057000000000004]}
'read0_power': [0.0553667],
'read1_power': [0.05177618],
'slew_hl': [0.1099853],
'slew_lh': [0.02568626],
'write0_power': [0.04517803],
'write1_power': [0.04449207]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.644147],
'delay_lh': [1.629815],
'leakage_power': 0.001542964,
'min_period': 4.688,
'read0_power': [16.28732],
'read1_power': [15.75155],
'slew_hl': [0.6722473],
'slew_lh': [0.3386347],
'write0_power': [18.545450000000002],
'write1_power': [16.81084]}
golden_data = {'delay_hl': [6.45408],
'delay_lh': [2.0787519999999997],
'leakage_power': 0.001177846,
'min_period': 9.688,
'read0_power': [7.088419],
'read1_power': [6.824107000000001],
'slew_hl': [0.7980976999999999],
'slew_lh': [0.3393389],
'write0_power': [5.982207],
'write1_power': [6.28866]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/22_psram_1bank_2mux_func_test.py
+10 -6
View File
@@ -11,8 +11,8 @@ import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_2mux_func_test")
class psram_1bank_2mux_func_test(openram_test):
@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?")
class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
@@ -35,10 +35,14 @@ class psram_1bank_2mux_func_test(openram_test):
num_words=64,
num_banks=1)
c.words_per_row=2
debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
c.recompute_sizes()
debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
compiler/tests/22_psram_1bank_4mux_func_test.py
+9 -5
View File
@@ -11,7 +11,7 @@ import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?")
class psram_1bank_4mux_func_test(openram_test):
def runTest(self):
@@ -35,10 +35,14 @@ class psram_1bank_4mux_func_test(openram_test):
num_words=256,
num_banks=1)
c.words_per_row=4
debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
c.recompute_sizes()
debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
compiler/tests/22_psram_1bank_8mux_func_test.py
+8 -4
View File
@@ -35,10 +35,14 @@ class psram_1bank_8mux_func_test(openram_test):
num_words=256,
num_banks=1)
c.words_per_row=8
debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
c.recompute_sizes()
debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
compiler/tests/22_psram_1bank_nomux_func_test.py
+8 -4
View File
@@ -35,10 +35,14 @@ class psram_1bank_nomux_func_test(openram_test):
num_words=32,
num_banks=1)
c.words_per_row=1
debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
c.recompute_sizes()
debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
compiler/tests/22_sram_1bank_2mux_func_test.py
+1
View File
@@ -30,6 +30,7 @@ class sram_1bank_2mux_func_test(openram_test):
num_words=64,
num_banks=1)
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
compiler/tests/22_sram_1bank_4mux_func_test.py
+1
View File
@@ -30,6 +30,7 @@ class sram_1bank_4mux_func_test(openram_test):
num_words=256,
num_banks=1)
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
compiler/tests/22_sram_1bank_8mux_func_test.py
+1
View File
@@ -33,6 +33,7 @@ class sram_1bank_8mux_func_test(openram_test):
num_words=256,
num_banks=1)
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
compiler/tests/22_sram_1bank_nomux_func_test.py
+1
View File
@@ -30,6 +30,7 @@ class sram_1bank_nomux_func_test(openram_test):
num_words=32,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
+1
View File
@@ -35,6 +35,7 @@ class psram_1bank_nomux_func_test(openram_test):
num_words=32,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Functional test for sram 1rw,1r with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
c.num_words,
c.words_per_row,
compiler/tests/23_lib_sram_model_test.py
+1
View File
@@ -23,6 +23,7 @@ class lib_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
compiler/tests/23_lib_sram_prune_test.py
+1
View File
@@ -32,6 +32,7 @@ class lib_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
compiler/tests/23_lib_sram_test.py
+1
View File
@@ -32,6 +32,7 @@ class lib_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
compiler/tests/24_lef_sram_test.py
+1
View File
@@ -23,6 +23,7 @@ class lef_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
compiler/tests/25_verilog_sram_test.py
+1
View File
@@ -22,6 +22,7 @@ class verilog_test(openram_test):
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
compiler/tests/27_worst_case_delay_test.py
+1 -1
View File
@@ -39,7 +39,7 @@ class worst_case_timing_sram_test(openram_test):
num_words=num_words,
num_banks=num_banks)
c.words_per_row=1
#c.compute_sizes()
c.recompute_sizes()
debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
word_size, num_words, num_banks))
s = sram(c, name="sram1")
compiler/tests/30_openram_test.py
+8 -7
View File
@@ -42,13 +42,14 @@ class openram_test(openram_test):
OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
cmd = "python3 {0}/openram.py -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(OPENRAM_HOME,
out_file,
out_path,
verbosity,
OPTS.tech_name,
out_path)
# Always perform code coverage
exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME)
cmd = "{0} -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(exe_name,
out_file,
out_path,
verbosity,
OPTS.tech_name,
out_path)
debug.info(1, cmd)
os.system(cmd)