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changed control signal names in bank select to accommodate multi-port changes in bank

This commit is contained in:
Michael Timothy Grimes 2018-08-19 00:00:42 -07:00
parent 19ca0d6c2a
commit 8e3dc332f3
2 changed files with 2 additions and 2 deletions
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2
compiler/modules/bank.py
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@ -639,7 +639,7 @@ class bank(design.design):
layer=data_pin.layer, layer=data_pin.layer,
offset=data_pin.center(), offset=data_pin.center(),
height=data_pin.height(), height=data_pin.height(),
width=data_pin.width()), width=data_pin.width())
def route_row_decoder(self): def route_row_decoder(self):

2
compiler/modules/bank_select.py
View File

@ -21,7 +21,7 @@ class bank_select(design.design):
# Number of control lines in the bus # Number of control lines in the bus
self.num_control_lines = 4 self.num_control_lines = 4
# The order of the control signals on the control bus: # The order of the control signals on the control bus:
self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"] self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
# These will be outputs of the gaters if this is multibank # These will be outputs of the gaters if this is multibank
self.control_signals = ["gated_"+str for str in self.input_control_signals] self.control_signals = ["gated_"+str for str in self.input_control_signals]