From 8e3dc332f3b8a1464e4be4b608b9f672940bc386 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Sun, 19 Aug 2018 00:00:42 -0700 Subject: [PATCH] changed control signal names in bank select to accommodate multi-port changes in bank --- compiler/modules/bank.py | 2 +- compiler/modules/bank_select.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 02030b46..dbfeebda 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -639,7 +639,7 @@ class bank(design.design): layer=data_pin.layer, offset=data_pin.center(), height=data_pin.height(), - width=data_pin.width()), + width=data_pin.width()) def route_row_decoder(self): diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index f89f16be..511e2e7c 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -21,7 +21,7 @@ class bank_select(design.design): # Number of control lines in the bus self.num_control_lines = 4 # The order of the control signals on the control bus: - self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"] + self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"] # These will be outputs of the gaters if this is multibank self.control_signals = ["gated_"+str for str in self.input_control_signals]