mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 11:08:01 +02:00
merge in wlbuf and begin work on 32kb memory
This commit is contained in:
jcirimel
@@ -21,35 +21,48 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, rows, cols, rbl, name, add_rbl=None):
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(name, rows, cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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# This is how many RBLs are added to THIS array
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if add_rbl == None:
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self.add_left_rbl = rbl[0]
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self.add_right_rbl = rbl[1]
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if rbl:
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self.rbl = rbl
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else:
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self.add_left_rbl = add_rbl[0]
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self.add_right_rbl = add_rbl[1]
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for a, b in zip(add_rbl, rbl):
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debug.check(a <= b,
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"Invalid number of RBLs for port configuration.")
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debug.check(sum(rbl) <= len(self.all_ports),
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self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
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# This specifies which RBL to put on the left or right
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# by port number
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# This could be an empty list
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if left_rbl != None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = [0]
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# This could be an empty list
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if right_rbl != None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[1] if len(self.all_ports) > 1 else []
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self.rbls = self.left_rbl + self.right_rbl
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debug.check(sum(self.rbl) == len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl),
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"Invalid number of RBLs for port configuration.")
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = 2 + sum(rbl)
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self.extra_rows = 2 + sum(self.rbl)
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# Two dummy cols plus replica if we add the column
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self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl
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self.extra_cols = 2 + len(self.left_rbl) + len(self.right_rbl)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@@ -89,42 +102,49 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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"""
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# Bitcell array
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self.bitcell_array = factory.create(module_type="bitcell_array",
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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cols=self.column_size,
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rows=self.row_size)
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self.add_mod(self.bitcell_array)
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# Replica bitlines
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self.replica_columns = {}
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for bit in range(self.add_left_rbl + self.add_right_rbl):
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# Creating left_rbl
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if bit < self.add_left_rbl:
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for port in self.all_ports:
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if port in self.left_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the top (where the bitcell array starts ) down
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replica_bit = self.left_rbl - bit
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# Creating right_rbl
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else:
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replica_bit = self.rbl[0] - port
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elif port in self.right_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the bottom up
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replica_bit = self.left_rbl + self.row_size + 1 + bit
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replica_bit = self.rbl[0] + self.row_size + port
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else:
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continue
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# If we have an odd numer on the bottom
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column_offset = self.left_rbl + 1
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self.replica_columns[bit] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[bit])
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# If there are bitcell end caps, replace the dummy cells on the edge of the bitcell array with end caps.
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column_offset = self.rbl[0] + 1
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self.replica_columns[port] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[port])
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try:
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end_caps_enabled = cell_properties.bitcell.end_caps
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except AttributeError:
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end_caps_enabled = False
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# Dummy row
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# Dummy row
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self.dummy_row = factory.create(module_type="dummy_array",
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.dummy_row)
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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@@ -134,8 +154,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.col_cap = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + self.add_left_rbl,
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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self.add_mod(self.col_cap)
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@@ -155,7 +175,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + self.add_left_rbl + self.column_size + self.add_right_rbl,
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl + 1) %2)
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self.add_mod(self.row_cap_right)
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@@ -166,7 +186,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="top")
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self.add_mod(self.col_cap_top)
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@@ -175,7 +195,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + self.add_left_rbl,
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="bottom")
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self.add_mod(self.col_cap_bottom)
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@@ -195,7 +215,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset = 1 + self.add_left_rbl + self.column_size + self.add_right_rbl,
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column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=0)
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self.add_mod(self.row_cap_right)
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@@ -221,94 +241,81 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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# Regular bitline names by port
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self.bitline_names = []
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# Replica bitlines by port
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self.rbl_bitline_names = []
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# Dummy bitlines by left/right
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self.dummy_col_bitline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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for loc in ["left", "right"]:
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self.dummy_col_bitline_names.append([])
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for port in self.all_ports:
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bitline_names = ["dummy_{0}_{1}".format(x, loc) for x in self.row_cap_left.get_bitline_names(port)]
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self.dummy_col_bitline_names[-1].extend(bitline_names)
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self.all_dummy_col_bitline_names = [x for sl in self.dummy_col_bitline_names for x in sl]
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for port in range(self.add_left_rbl + self.add_right_rbl):
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left_names=["rbl_bl_{0}_{1}".format(x, port) for x in self.all_ports]
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right_names=["rbl_br_{0}_{1}".format(x, port) for x in self.all_ports]
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bitline_names = [x for t in zip(left_names, right_names) for x in t]
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self.rbl_bitline_names.append(bitline_names)
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# The bit is which port the RBL is for
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for bit in self.rbls:
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for port in self.all_ports:
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self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
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for port in self.all_ports:
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self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
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# Make a flat list too
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self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
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for port in self.all_ports:
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bitline_names = self.bitcell_array.get_bitline_names(port)
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self.bitline_names.append(bitline_names)
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self.bitline_names = self.bitcell_array.bitline_names
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.add_pin_list(self.dummy_col_bitline_names[0], "INOUT")
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for port in range(self.add_left_rbl):
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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self.add_pin_list(self.all_bitline_names, "INOUT")
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for port in range(self.add_left_rbl, self.add_left_rbl + self.add_right_rbl):
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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self.add_pin_list(self.dummy_col_bitline_names[1], "INOUT")
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for port in self.left_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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self.add_pin_list(self.all_bitline_names, "INOUT")
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for port in self.right_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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def add_wordline_pins(self):
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# Regular wordlines by port
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self.wordline_names = []
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# Replica wordlines by port
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self.rbl_wordline_names = []
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# Dummy wordlines by bot/top
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self.dummy_row_wordline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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dummy_row_wordline_names = ["dummy_" + x for x in self.col_cap.get_wordline_names()]
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for loc in ["bot", "top"]:
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wordline_names = ["{0}_{1}".format(wl_name, loc) for wl_name in dummy_row_wordline_names]
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self.dummy_row_wordline_names.append(wordline_names)
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self.all_dummy_row_wordline_names = [x for sl in self.dummy_row_wordline_names for x in sl]
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for port in range(self.left_rbl + self.right_rbl):
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if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports]
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self.rbl_wordline_names.append(wordline_names)
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else:
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for x in self.all_ports:
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wordline_names = []
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wordline_names.append("rbl_wl0_{0}_{1}".format(x, port))
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wordline_names.append("rbl_wl1_{0}_{1}".format(x, port))
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self.rbl_wordline_names.append(wordline_names)
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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# Wordlines to ground
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self.gnd_wordline_names = []
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for port in self.all_ports:
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wordline_names = self.bitcell_array.get_wordline_names(port)
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self.wordline_names.append(wordline_names)
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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for bit in self.all_ports:
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if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
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else:
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self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit))
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self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit))
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self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names[0])
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for p in range(self.left_rbl):
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self.replica_array_wordline_names.extend(self.rbl_wordline_names[p])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for p in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.replica_array_wordline_names.extend(self.rbl_wordline_names[p])
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names[1])
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.add_pin_list(self.dummy_row_wordline_names[0], "INPUT")
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for port in range(self.left_rbl):
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self.add_pin_list(self.rbl_wordline_names[port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.add_pin_list(self.rbl_wordline_names[port], "INPUT")
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.add_pin_list(self.dummy_row_wordline_names[1], "INPUT")
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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else:
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * 2)
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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self.replica_array_wordline_names.extend(["gnd"] *2)
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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@@ -331,68 +338,77 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# Replica columns
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self.replica_col_insts = []
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for port in range(self.add_left_rbl + self.add_right_rbl):
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in range(self.left_rbl + self.right_rbl):
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies)
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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self.connect_inst(self.all_bitline_names
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+ self.dummy_row_wordline_names[0]
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+ self.supplies)
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap))
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self.connect_inst(self.all_bitline_names
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+ self.dummy_row_wordline_names[1]
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+ self.supplies)
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self.connect_inst(["gnd"] * len(self.col_cap.get_wordline_names()) + self.supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(self.dummy_col_bitline_names[0] + self.replica_array_wordline_names + self.supplies)
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(self.dummy_col_bitline_names[1] + self.replica_array_wordline_names + self.supplies)
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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else:
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="col_cap_bottom",
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap_bottom))
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self.connect_inst(self.all_bitline_names
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+ self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="col_cap_top",
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self.connect_inst(self.all_bitline_names + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap_top))
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self.connect_inst(self.all_bitline_names
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+ self.supplies)
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self.connect_inst(self.all_bitline_names + self.supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="row_cap_left",
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="row_cap_right",
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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def create_layout(self):
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# We will need unused wordlines grounded, so we need to know their layer
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pin = self.cell.get_pin(self.cell.get_all_wl_names()[0])
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pin_layer = pin.layer
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self.unused_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
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self.unused_offset = vector(self.unused_pitch, 0)
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# Add extra width on the left and right for the unused WLs
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
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self.width = (self.column_size + self.extra_cols) * self.cell.width
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self.width = (self.column_size + self.extra_cols) * self.cell.width + 2 * self.unused_pitch
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else:
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self.width = self.row_cap_left.top_corner.width + self.row_cap_right.top_corner.width + (self.col_cap_top.colend1.width + self.col_cap_top.colend2.width) * (self.column_size + self.extra_cols) - self.col_cap_top.colend2.width
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self.width = self.row_cap_left.width + self.row_cap_right.width + self.col_cap_top.width
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for rbl in range(self.rbl[0] + self.rbl[1]):
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self.width += self.replica_col_insts[rbl].width
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self.height = self.row_cap_left.height
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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@@ -404,54 +420,79 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
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self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
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# Everything is computed with the main array at (0, 0) to start
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self.bitcell_array_inst.place(offset=[0, 0])
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# Everything is computed with the main array at (self.unused_pitch, 0) to start
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self.bitcell_array_inst.place(offset=self.unused_offset)
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self.add_replica_columns()
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self.add_end_caps()
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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self.translate_all(self.bitcell_offset.scale(-1 - self.add_left_rbl, -1 - self.left_rbl))
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array_offset = self.bitcell_offset.scale(1 + len(self.left_rbl), 1 + self.rbl[0])
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self.translate_all(array_offset.scale(-1, -1))
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self.add_layout_pins()
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self.route_unused_wordlines()
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self.add_boundary()
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self.DRC_LVS()
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def get_main_array_top(self):
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return self.bitcell_array_inst.uy()
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def get_main_array_bottom(self):
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return self.bitcell_array_inst.by()
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def get_main_array_left(self):
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return self.bitcell_array_inst.lx()
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def get_main_array_right(self):
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return self.bitcell_array_inst.rx()
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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offsets = [x + self.bitcell_array_inst.lx() for x in self.bitcell_array.get_column_offsets()]
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return offsets
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def add_replica_columns(self):
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""" Add replica columns on left and right of array """
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end_caps_enabled = cell_properties.bitcell.end_caps
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# Grow from left to right, toward the array
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for bit in range(self.add_left_rbl):
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for bit, port in enumerate(self.left_rbl):
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if not end_caps_enabled:
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offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1) + self.strap_offset.scale(-self.add_left_rbl + bit, 0)
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offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1) + self.strap_offset.scale(-len(self.left_rbl) + bit, 0) + self.unused_offset
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else:
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offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(-self.add_left_rbl + bit, 0)
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offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(-len(self.left_rbl) + bit, 0) + self.unused_offset
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self.replica_col_insts[bit].place(offset)
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# Grow to the right of the bitcell array, array outward
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for bit in range(self.add_right_rbl):
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for bit, port in enumerate(self.right_rbl):
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if not end_caps_enabled:
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1) + self.strap_offset.scale(bit, -self.left_rbl - 1)
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1) + self.strap_offset.scale(bit, -self.rbl[0] - 1)
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else:
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.left_rbl - 1)
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.rbl[0] - 1)
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self.replica_col_insts[self.add_left_rbl + bit].place(offset)
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self.replica_col_insts[len(self.left_rbl) + bit].place(offset)
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# Replica dummy rows
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# Add the dummy rows even if we aren't adding the replica column to this bitcell array
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# These grow up, toward the array
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for bit in range(self.left_rbl):
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self.dummy_row_replica_insts[bit].place(offset=self.bitcell_offset.scale(0, -self.left_rbl + bit + (-self.left_rbl + bit) % 2),
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mirror="MX" if (-self.left_rbl + bit) % 2 else "R0")
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for bit in range(self.rbl[0]):
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dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
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self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
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mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
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# These grow up, away from the array
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for bit in range(self.right_rbl):
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self.dummy_row_replica_insts[self.left_rbl + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(),
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mirror="MX" if bit % 2 else "R0")
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for bit in range(self.rbl[1]):
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dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
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self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
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mirror="MX" if bit % 2 else "R0")
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def add_end_caps(self):
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""" Add dummy cells or end caps around the array """
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@@ -459,43 +500,43 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# FIXME: These depend on the array size itself
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# Far top dummy row (first row above array is NOT flipped)
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flip_dummy = self.right_rbl % 2
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flip_dummy = self.rbl[1] % 2
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if not end_caps_enabled:
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dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul()
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dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
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else:
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dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul()
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dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# FIXME: These depend on the array size itself
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.left_rbl + 1) % 2
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flip_dummy = (self.rbl[0] + 1) % 2
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||||
if not end_caps_enabled:
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dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy)
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||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy) + self.unused_offset
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else:
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||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - (self.col_end_offset.y/self.cell.height) + flip_dummy)
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dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - (self.col_end_offset.y/self.cell.height) + flip_dummy) + self.unused_offset
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self.dummy_row_insts[0].place(offset=dummy_row_offset,
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||||
mirror="MX" if flip_dummy else "R0")
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# Far left dummy col
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||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
if not end_caps_enabled:
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||||
dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1)
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dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -len(self.left_rbl) - 1)
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else:
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dummy_col_offset = self.bitcell_offset.scale(-(self.add_left_rbl*(1+self.strap_offset.x/self.cell.width)) - (self.row_end_offset.x/self.cell.width), -self.left_rbl - (self.col_end_offset.y/self.cell.height))
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dummy_col_offset = self.bitcell_offset.scale(-(len(self.left_rbl)*(1+self.strap_offset.x/self.cell.width)) - (self.row_end_offset.x/self.cell.width), -len(self.left_rbl) - (self.col_end_offset.y/self.cell.height))
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||||
|
||||
self.dummy_col_insts[0].place(offset=dummy_col_offset)
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||||
# Far right dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
if not end_caps_enabled:
|
||||
dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl*(1+self.strap_offset.x/self.cell.width), -self.left_rbl - 1) + self.bitcell_array_inst.lr()
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl)*(1+self.strap_offset.x/self.cell.width), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
|
||||
else:
|
||||
dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl*(1+self.strap_offset.x/self.cell.width), -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.bitcell_array_inst.lr()
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl)*(1+self.strap_offset.x/self.cell.width), -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.bitcell_array_inst.lr()
|
||||
|
||||
self.dummy_col_insts[1].place(offset=dummy_col_offset)
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
|
||||
# All wordlines
|
||||
# Main array wl and bl/br
|
||||
for pin_name in self.all_wordline_names:
|
||||
@@ -506,6 +547,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in self.all_bitline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
@@ -515,21 +557,12 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
# Dummy wordlines
|
||||
for (names, inst) in zip(self.dummy_row_wordline_names, self.dummy_row_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
# It's always a single row
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
||||
# even though the column is in another local bitcell array)
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
continue
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
@@ -538,14 +571,16 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
height=pin.height())
|
||||
|
||||
# Replica bitlines
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
for (bl_name, pin_name) in zip(names, self.replica_columns[0].all_bitline_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
if len(self.rbls) > 0:
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
|
||||
for (bl_name, pin_name) in zip(names, pin_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
# vdd/gnd are only connected in the perimeter cells
|
||||
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
|
||||
@@ -557,85 +592,12 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
for pin in pin_list:
|
||||
self.add_power_pin(name=pin_name,
|
||||
loc=pin.center(),
|
||||
directions=("V", "V"),
|
||||
start_layer=pin.layer)
|
||||
|
||||
for inst in self.replica_col_insts:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
if inst:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def get_rbl_wordline_names(self, port=None):
|
||||
"""
|
||||
Return the ACTIVE WL for the given RBL port.
|
||||
Inactive will be set to gnd.
|
||||
"""
|
||||
if port == None:
|
||||
return self.all_rbl_wordline_names
|
||||
else:
|
||||
return self.rbl_wordline_names[port]
|
||||
|
||||
def get_rbl_bitline_names(self, port=None):
|
||||
""" Return the BL for the given RBL port """
|
||||
if port == None:
|
||||
return self.all_rbl_bitline_names
|
||||
else:
|
||||
return self.rbl_bitline_names[port]
|
||||
|
||||
def get_bitline_names(self, port=None):
|
||||
""" Return the regular bitlines for the given port or all"""
|
||||
if port == None:
|
||||
return self.all_bitline_names
|
||||
else:
|
||||
return self.bitline_names[port]
|
||||
|
||||
def get_all_bitline_names(self):
|
||||
""" Return ALL the bitline names (including dummy and rbl) """
|
||||
temp = []
|
||||
temp.extend(self.get_dummy_bitline_names(0))
|
||||
if self.add_left_rbl > 0:
|
||||
temp.extend(self.get_rbl_bitline_names(0))
|
||||
temp.extend(self.get_bitline_names())
|
||||
if self.add_right_rbl > 0:
|
||||
temp.extend(self.get_rbl_bitline_names(self.add_left_rbl))
|
||||
temp.extend(self.get_dummy_bitline_names(1))
|
||||
return temp
|
||||
|
||||
def get_wordline_names(self, port=None):
|
||||
""" Return the regular wordline names """
|
||||
if port == None:
|
||||
return self.all_wordline_names
|
||||
else:
|
||||
return self.wordline_names[port]
|
||||
|
||||
def get_all_wordline_names(self, port=None):
|
||||
""" Return all the wordline names """
|
||||
temp = []
|
||||
temp.extend(self.get_dummy_wordline_names(0))
|
||||
temp.extend(self.get_rbl_wordline_names(0))
|
||||
if port == None:
|
||||
temp.extend(self.all_wordline_names)
|
||||
else:
|
||||
temp.extend(self.wordline_names[port])
|
||||
if len(self.all_ports) > 1:
|
||||
temp.extend(self.get_rbl_wordline_names(1))
|
||||
temp.extend(self.get_dummy_wordline_names(1))
|
||||
return temp
|
||||
|
||||
def get_dummy_wordline_names(self, port=None):
|
||||
"""
|
||||
Return the ACTIVE WL for the given dummy port.
|
||||
"""
|
||||
if port == None:
|
||||
return self.all_dummy_row_wordline_names
|
||||
else:
|
||||
return self.dummy_row_wordline_names[port]
|
||||
|
||||
def get_dummy_bitline_names(self, port=None):
|
||||
""" Return the BL for the given dummy port """
|
||||
if port == None:
|
||||
return self.all_dummy_col_bitline_names
|
||||
else:
|
||||
return self.dummy_col_bitline_names[port]
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
# Dynamic Power from Bitline
|
||||
@@ -653,6 +615,37 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
cell_power.leakage * self.column_size * self.row_size)
|
||||
return total_power
|
||||
|
||||
def route_unused_wordlines(self):
|
||||
""" Connect the unused RBL and dummy wordlines to gnd """
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
|
||||
# This grounds all the dummy row word lines
|
||||
for inst in self.dummy_row_insts:
|
||||
for wl_name in self.col_cap.get_wordline_names():
|
||||
self.ground_pin(inst, wl_name)
|
||||
|
||||
# Ground the unused replica wordlines
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
self.ground_pin(inst, pin_name)
|
||||
|
||||
def ground_pin(self, inst, name):
|
||||
pin = inst.get_pin(name)
|
||||
pin_layer = pin.layer
|
||||
|
||||
left_pin_loc = vector(self.dummy_col_insts[0].lx(), pin.cy())
|
||||
right_pin_loc = vector(self.dummy_col_insts[1].rx(), pin.cy())
|
||||
|
||||
# Place the pins a track outside of the array
|
||||
left_loc = left_pin_loc - vector(self.unused_pitch, 0)
|
||||
right_loc = right_pin_loc + vector(self.unused_pitch, 0)
|
||||
self.add_power_pin("gnd", left_loc, directions=("H", "H"))
|
||||
self.add_power_pin("gnd", right_loc, directions=("H", "H"))
|
||||
|
||||
# Add a path to connect to the array
|
||||
self.add_path(pin_layer, [left_loc, left_pin_loc])
|
||||
self.add_path(pin_layer, [right_loc, right_pin_loc])
|
||||
|
||||
def gen_bl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
height = 0
|
||||
@@ -663,23 +656,28 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def get_wordline_cin(self):
|
||||
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
||||
# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
||||
bitcell_wl_cin = self.cell.get_wl_cin()
|
||||
total_cin = bitcell_wl_cin * self.column_size
|
||||
return total_cin
|
||||
|
||||
def graph_exclude_bits(self, targ_row, targ_col):
|
||||
"""Excludes bits in column from being added to graph except target"""
|
||||
def graph_exclude_bits(self, targ_row=None, targ_col=None):
|
||||
"""
|
||||
Excludes bits in column from being added to graph except target
|
||||
"""
|
||||
self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
||||
|
||||
def graph_exclude_replica_col_bits(self):
|
||||
"""Exclude all replica/dummy cells in the replica columns except the replica bit."""
|
||||
"""
|
||||
Exclude all replica/dummy cells in the replica columns except the replica bit.
|
||||
"""
|
||||
|
||||
for port in range(self.left_rbl + self.right_rbl):
|
||||
for port in self.left_rbl + self.right_rbl:
|
||||
self.replica_columns[port].exclude_all_but_replica()
|
||||
|
||||
def get_cell_name(self, inst_name, row, col):
|
||||
"""Gets the spice name of the target bitcell."""
|
||||
"""
|
||||
Gets the spice name of the target bitcell.
|
||||
"""
|
||||
return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col)
|
||||
|
||||
def clear_exclude_bits(self):
|
||||
"""
|
||||
Clears the bit exclusions
|
||||
"""
|
||||
self.bitcell_array.init_graph_params()
|
||||
|
||||
Reference in New Issue
Block a user