luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

add fix for cypress sp wls

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2026-04-28 17:19:54 -07:00
parent 5077282180
commit 88241ca685
8 changed files with 35 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_base_array.py
+5 -3
View File
@@ -121,13 +121,15 @@ class bitcell_base_array(design):
def get_all_wordline_names(self, port=None):
""" Return all the wordline names """
temp = []
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
if len(self.all_ports) > 0:
temp.extend(self.get_rbl_wordline_names(0))
if port == None:
temp.extend(self.all_wordline_names)
else:
temp.extend(self.wordline_names[port])
temp.extend(self.get_rbl_wordline_names(0))
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
return temp