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https://github.com/VLSIDA/OpenRAM.git
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various refactor changes
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@@ -73,12 +73,23 @@ class row_cap_array(bitcell_base_array):
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.get_all_wl_names()
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#row_list = self.cell.get_all_wl_names()
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#for row in range(0, self.row_size - 2):
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# for cell_row in row_list:
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# wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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# self.add_layout_pin(text=cell_row + "_{0}".format(row),
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# layer=wl_pin.layer,
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# offset=wl_pin.ll().scale(0, 1),
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# width=self.width,
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# height=wl_pin.height())
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wl_names = self.cell.get_all_wl_names()
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for row in range(0, self.row_size - 2):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row + "_{0}".format(row),
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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