diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index a2976235..df74b8b9 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -204,10 +204,12 @@ class capped_replica_bitcell_array(bitcell_base_array): self.add_end_caps() + ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts])) + + self.translate_all(ll) self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts]) self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts]) - self.add_layout_pins() self.route_supplies() @@ -219,6 +221,7 @@ class capped_replica_bitcell_array(bitcell_base_array): self.translate_all(ll) + self.add_layout_pins() self.add_boundary() self.DRC_LVS() diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 26554ca6..9f9a64da 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -82,17 +82,21 @@ class col_cap_array(bitcell_base_array): def add_layout_pins(self): """ Add the layout pins """ - column_list = self.cell.get_all_bitline_names() - + bitline_names = self.cell.get_all_bitline_names() for col in range(self.column_size): - for cell_column in column_list: - bl_pin = self.cell_inst[0, col].get_pin(cell_column) - self.add_layout_pin(text=cell_column + "_{0}".format(col), + for port in self.all_ports: + bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port]) + self.add_layout_pin(text="bl_{0}_{1}".format(port, col), layer=bl_pin.layer, offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), height=self.height) - + br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1]) + self.add_layout_pin(text="br_{0}_{1}".format(port, col), + layer=br_pin.layer, + offset=br_pin.ll().scale(1, 0), + width=br_pin.width(), + height=self.height) # Add vdd/gnd via stacks for row in range(self.row_size): for col in range(self.column_size): diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index 3c91932b..4febdde3 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -73,12 +73,23 @@ class row_cap_array(bitcell_base_array): def add_layout_pins(self): """ Add the layout pins """ - row_list = self.cell.get_all_wl_names() + #row_list = self.cell.get_all_wl_names() + #for row in range(0, self.row_size - 2): + # for cell_row in row_list: + # wl_pin = self.cell_inst[row, 0].get_pin(cell_row) + # self.add_layout_pin(text=cell_row + "_{0}".format(row), + # layer=wl_pin.layer, + # offset=wl_pin.ll().scale(0, 1), + # width=self.width, + # height=wl_pin.height()) + + wl_names = self.cell.get_all_wl_names() + for row in range(0, self.row_size - 2): - for cell_row in row_list: - wl_pin = self.cell_inst[row, 0].get_pin(cell_row) - self.add_layout_pin(text=cell_row + "_{0}".format(row), + for port in self.all_ports: + wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port]) + self.add_layout_pin(text="wl_{0}_{1}".format(port, row), layer=wl_pin.layer, offset=wl_pin.ll().scale(0, 1), width=self.width, diff --git a/technology/sky130/custom/sky130_capped_replica_bitcell_array.py b/technology/sky130/custom/sky130_capped_replica_bitcell_array.py index 49868bbe..dfe9a727 100644 --- a/technology/sky130/custom/sky130_capped_replica_bitcell_array.py +++ b/technology/sky130/custom/sky130_capped_replica_bitcell_array.py @@ -23,3 +23,29 @@ class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_b def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""): super().__init__(rows, cols, rbl, left_rbl, right_rbl, name) + def add_layout_pins(self): + for used_name, base_name in zip(self.used_wordline_names, self.dummy_col_insts[0].mod.all_wordline_names): + pin = self.dummy_col_insts[0].get_pin(base_name) + + pin_offset = pin.ll().scale(0, 1) + pin_width = self.width + pin_height = pin.height() + + self.add_layout_pin(text=used_name, + layer=pin.layer, + offset=pin_offset, + width=pin_width, + height=pin_height) + + for used_name, pin_name in zip(self.bitline_pin_list, self.dummy_row_insts[0].mod.all_bitline_names): + pin = self.dummy_row_insts[0].get_pin(pin_name) + pin_offset = pin.ll().scale(1, 0) + pin_width = pin.width() + pin_height = self.height + self.add_layout_pin(text=used_name, + layer=pin.layer, + offset=pin_offset, + width=pin_width, + height=pin_height) + + diff --git a/technology/sky130/custom/sky130_col_cap_array.py b/technology/sky130/custom/sky130_col_cap_array.py index eb44bc81..70ca69a3 100644 --- a/technology/sky130/custom/sky130_col_cap_array.py +++ b/technology/sky130/custom/sky130_col_cap_array.py @@ -37,12 +37,18 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array): def create_instances(self): self.all_inst={} self.cell_inst={} - - bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \ - + [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\ - + [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \ - + [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)] + if self.location == "top": + bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \ + + [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\ + + [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \ + + [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)] + elif self.location == "bottom": + bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True, mirror="MX")] \ + + [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False, mirror="MX")]\ + + [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="XY")] \ + + [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False, mirror="MX")] + bit_row = pattern.rotate_list(bit_row, self.column_offset * 2) bit_block = [] pattern.append_row_to_block(bit_block, bit_row) @@ -84,4 +90,4 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array): self.add_layout_pins() self.add_boundary() - self.DRC_LVS() \ No newline at end of file + self.DRC_LVS() diff --git a/technology/sky130/custom/sky130_row_cap_array.py b/technology/sky130/custom/sky130_row_cap_array.py index b0754896..24e85585 100644 --- a/technology/sky130/custom/sky130_row_cap_array.py +++ b/technology/sky130/custom/sky130_row_cap_array.py @@ -23,7 +23,7 @@ class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array): self.location = location def add_modules(self): """ Add the modules used in this design """ - if self.column_offset == 0: + if self.location == "left": self.top_corner = factory.create(module_type="corner", location="ul") self.bottom_corner =factory.create(module_type="corner", location="ll") #self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica") @@ -44,18 +44,25 @@ class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array): self.cell_inst={} bit_block = [] - top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="XY") - bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False) - rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True) - rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True, mirror="XY") - pattern.append_row_to_block(bit_block, [top_corner]) + if self.location == "left": + top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="MY") + bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="XY") + rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True, mirror="XY") + rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True, mirror="MY") + elif self.location == "right": + top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False) + bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="MX") + rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True, mirror="MX") + rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True) + + pattern.append_row_to_block(bit_block, [bottom_corner]) for row in range(1,self.row_size-1): if row % 2 == 0: pattern.append_row_to_block(bit_block, [rowend]) else: pattern.append_row_to_block(bit_block, [rowenda]) - pattern.append_row_to_block(bit_block, [bottom_corner]) + pattern.append_row_to_block(bit_block, [top_corner]) self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}") self.pattern.connect_array_raw()