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various refactor changes
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@@ -204,10 +204,12 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_end_caps()
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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self.translate_all(ll)
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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self.add_layout_pins()
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self.route_supplies()
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@@ -219,6 +221,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.translate_all(ll)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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