luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

various refactor changes

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2023-08-28 12:31:55 -07:00
parent ba51149dce
commit 8794070ebc
6 changed files with 81 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/capped_replica_bitcell_array.py
+4 -1
View File
@@ -204,10 +204,12 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_end_caps()
ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
self.translate_all(ll)
self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
self.add_layout_pins()
self.route_supplies()
@@ -219,6 +221,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.translate_all(ll)
self.add_layout_pins()
self.add_boundary()
self.DRC_LVS()
compiler/modules/col_cap_array.py
+10 -6
View File
@@ -82,17 +82,21 @@ class col_cap_array(bitcell_base_array):
def add_layout_pins(self):
""" Add the layout pins """
column_list = self.cell.get_all_bitline_names()
bitline_names = self.cell.get_all_bitline_names()
for col in range(self.column_size):
for cell_column in column_list:
bl_pin = self.cell_inst[0, col].get_pin(cell_column)
self.add_layout_pin(text=cell_column + "_{0}".format(col),
for port in self.all_ports:
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
layer=bl_pin.layer,
offset=bl_pin.ll().scale(1, 0),
width=bl_pin.width(),
height=self.height)
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
self.add_layout_pin(text="br_{0}_{1}".format(port, col),
layer=br_pin.layer,
offset=br_pin.ll().scale(1, 0),
width=br_pin.width(),
height=self.height)
# Add vdd/gnd via stacks
for row in range(self.row_size):
for col in range(self.column_size):
compiler/modules/row_cap_array.py
+15 -4
View File
@@ -73,12 +73,23 @@ class row_cap_array(bitcell_base_array):
def add_layout_pins(self):
""" Add the layout pins """
row_list = self.cell.get_all_wl_names()
#row_list = self.cell.get_all_wl_names()
#for row in range(0, self.row_size - 2):
# for cell_row in row_list:
# wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
# self.add_layout_pin(text=cell_row + "_{0}".format(row),
# layer=wl_pin.layer,
# offset=wl_pin.ll().scale(0, 1),
# width=self.width,
# height=wl_pin.height())
wl_names = self.cell.get_all_wl_names()
for row in range(0, self.row_size - 2):
for cell_row in row_list:
wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
self.add_layout_pin(text=cell_row + "_{0}".format(row),
for port in self.all_ports:
wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
layer=wl_pin.layer,
offset=wl_pin.ll().scale(0, 1),
width=self.width,