diff --git a/compiler/base/design.py b/compiler/base/design.py
index 2c3ba2ea..159861f6 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -26,8 +26,14 @@ class design(hierarchy_design):
         # This allows us to use different GDS/spice circuits for hard cells instead of the default ones
         # Except bitcell names are generated automatically by the globals.py setup_bitcells routines
         # depending on the number of ports.
+
         if name in props.names:
-            cell_name = props.names[name]
+            if isinstance(name , list):
+                num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
+                cell_name = props.names[name][num_ports]
+            else:
+                cell_name = props.name[name]
+
         elif not cell_name:
             cell_name = name
         super().__init__(name, cell_name)