From 118b2b1215a8f7ae35b62c3d318c9d7dc470abff Mon Sep 17 00:00:00 2001
From: jcirimel <jcirimel@ucsc.edu>
Date: Tue, 20 Oct 2020 03:15:34 -0700
Subject: [PATCH 1/3] change bitline names to bl br for single port

---
 compiler/base/custom_cell_properties.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index 2e21c1ec..e02ffbe8 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -43,8 +43,8 @@ class _bitcell:
     def _default():
         axis = _mirror_axis(True, False)
 
-        cell_s8_6t = _cell({'bl' : 'bl0',
-                            'br' : 'bl1',
+        cell_s8_6t = _cell({'bl' : 'bl',
+                            'br' : 'br',
                             'wl': 'wl'})
 
         cell_6t = _cell({'bl' : 'bl',

From 520b4966114ef3823be4e5ace3374a038bb40749 Mon Sep 17 00:00:00 2001
From: jcirimel <jcirimel@ucsc.edu>
Date: Wed, 18 Nov 2020 10:47:05 -0800
Subject: [PATCH 2/3] check for cell prop names list

---
 compiler/base/design.py | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/compiler/base/design.py b/compiler/base/design.py
index f90ea12c..c087576f 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -26,10 +26,16 @@ class design(hierarchy_design):
         # This allows us to use different GDS/spice circuits for hard cells instead of the default ones
         # Except bitcell names are generated automatically by the globals.py setup_bitcells routines
         # depending on the number of ports.
+
         if name in props.names:
-            cell_name = props.names[name]
+            if isinstance(name , list):
+                num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
+                cell_name = props.names[name][num_ports]
+            else:
+                cell_name = props.name[name]
+
         elif not cell_name:
-            cell_name = name
+            cell_name = nacell_name = props.name[name]
         super().__init__(name, cell_name)
 
         # This means it is a custom cell.

From 50a0b88ef890c5c511f389516119df63ba4b708c Mon Sep 17 00:00:00 2001
From: jcirimel <jcirimel@ucsc.edu>
Date: Wed, 18 Nov 2020 11:02:40 -0800
Subject: [PATCH 3/3] fix typo

---
 compiler/base/design.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/base/design.py b/compiler/base/design.py
index c087576f..d124970c 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -35,7 +35,7 @@ class design(hierarchy_design):
                 cell_name = props.name[name]
 
         elif not cell_name:
-            cell_name = nacell_name = props.name[name]
+            cell_name = name
         super().__init__(name, cell_name)
 
         # This means it is a custom cell.