From 83b25138d0a4d5b17741017a12eb545d1d9f301b Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 3 Apr 2023 10:11:49 -0700 Subject: [PATCH] apply 14* standard to 15_local tests --- .../15_local_bitcell_array_1rw_1r_test.py | 59 ------------------- .../tests/15_local_bitcell_array_1rw_test.py | 51 ---------------- ...local_bitcell_array_leftrbl_1rw_1r_test.py | 1 + ...ocal_bitcell_array_rightrbl_1rw_1r_test.py | 1 + 4 files changed, 2 insertions(+), 110 deletions(-) delete mode 100755 compiler/tests/15_local_bitcell_array_1rw_1r_test.py delete mode 100755 compiler/tests/15_local_bitcell_array_1rw_test.py diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py deleted file mode 100755 index 8f9cebc0..00000000 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -# @unittest.skip("SKIPPING 05_local_bitcell_array_test") -class local_bitcell_array_1rw_1r_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 4x4 local array for 1rw1r cell without replica columns or dummy rows") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with dummy rows only") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with left replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with right replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with both replica columns") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_1rw_test.py b/compiler/tests/15_local_bitcell_array_1rw_test.py deleted file mode 100755 index bfe14b45..00000000 --- a/compiler/tests/15_local_bitcell_array_1rw_test.py +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -# @unittest.skip("SKIPPING 05_local_bitcell_array_test") -class local_bitcell_array_1rw_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 0 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column or dummy row") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column but with dummy row") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py index 0e1f2918..65be2de1 100755 --- a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class local_bitcell_array_leftrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py index 88c0099d..cc392587 100755 --- a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class local_bitcell_array_rightrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args()