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https://github.com/VLSIDA/OpenRAM.git
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fixed decode lvs
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@@ -90,8 +90,9 @@ class rom_precharge_array(design):
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def add_pins(self):
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for col in range(self.cols):
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self.add_pin("pre_bl{0}_out".format(col), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gate", "INPUT")
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self.add_pin("vdd", "POWER")
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def create_instances(self):
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self.array_insts = []
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@@ -164,7 +165,7 @@ class rom_precharge_array(design):
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# self.vdd = self.add_layout_pin_segment_center("vdd", self.supply_layer, start, end)
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# vdd = [self.pmos_insts[i].get_pin("vdd") for i in range(self.cols)]routeroute_horizon_horizon
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self.route_horizontal_pins("vdd", insts=self.pmos_insts)
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self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer)
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