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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
fixed decode lvs
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@@ -245,8 +245,7 @@ class rom_decoder(design):
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# self.add_segment_center(self.inv_route_layer, addr_bar_middle + vector(0, self.inv_route_width * 0.5), addr_bar_out_pin.center() + vector(0, self.inv_route_width * 0.5), self.inv_route_width)
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def route_supplies(self):
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minwidth = drc["minwidth_{}".format(self.inv_route_layer)]
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pitch = drc["{0}_to_{0}".format(self.inv_route_layer)]
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self.copy_layout_pin(self.array_inst, "vdd")
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self.copy_layout_pin(self.wordline_buf_inst, "vdd")
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self.copy_layout_pin(self.buf_inst, "vdd")
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@@ -255,9 +254,8 @@ class rom_decoder(design):
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self.copy_layout_pin(self.wordline_buf_inst, "gnd")
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self.copy_layout_pin(self.buf_inst, "gnd")
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# Extend nwells to connect with eachother
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self.extend_wells()
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# self.extend_wells()
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def extend_wells(self):
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@@ -272,11 +270,10 @@ class rom_decoder(design):
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self.add_label(text="well_left", layer="nwell", offset=offset)
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vdd_pins=self.buf_inst.get_pins("vdd").copy()
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print(vdd_pins)
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well_by = vdd_pins[1].cy()
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well_ll = vector(precharge_well_lx, well_by)
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self.add_rect(layer="nwell", offset=well_ll, height = self.array_inst.by() - well_by, width=precharge_well_rx - precharge_well_lx)
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well_by = vdd_pins[0].cy()
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# well_ll = vector(precharge_well_lx, well_by)
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well_ll = vector(self.buf_inst.rx(), well_by)
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# self.add_rect(layer="nwell", offset=well_ll, height = self.array_inst.by() - well_by, width=precharge_well_rx - self.buf_inst.rx())
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