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sky130 rba done

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jcirimel
2020-09-30 07:34:05 -07:00
parent 3dd72cdeac
commit 7cbf456a4f
10 changed files with 1949 additions and 97 deletions
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compiler/modules/dummy_array.py
+24 -10
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@@ -5,6 +5,8 @@
#
from bitcell_base_array import bitcell_base_array
from sram_factory import factory
from tech import GDS,layer,drc,parameter,cell_properties
from tech import cell_properties as props
from globals import OPTS
@@ -38,21 +40,33 @@ class dummy_array(bitcell_base_array):
def add_modules(self):
""" Add the modules used in this design """
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
self.cell = factory.create(module_type="bitcell")
else:
self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1")
self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a")
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
self.add_mod(self.dummy_cell2)
self.add_mod(self.dummy_cell)
self.cell = factory.create(module_type="bitcell")
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
else:
from tech import custom_cell_arrangement
custom_cell_arrangement(self)
def input_load(self):
wl_wire = self.gen_wl_wire()
return wl_wire.return_input_cap()