diff --git a/compiler/custom/s8_col_end.py b/compiler/custom/s8_col_end.py index a6961027..827692f0 100644 --- a/compiler/custom/s8_col_end.py +++ b/compiler/custom/s8_col_end.py @@ -21,8 +21,8 @@ class s8_col_end(design.design): type_list = [] if version == "colend": - self.name = "s8sram16x16_colend" - structure = "s8sram16x16_colend\x00" + self.name = "s8sram16x16_colenda" + structure = "s8sram16x16_colenda\x00" elif version == "colend_p_cent": self.name = "s8sram16x16_colend_p_cent" structure = "s8sram16x16_colend_p_cent\x00" diff --git a/compiler/custom/s8_corner.py b/compiler/custom/s8_corner.py index bb4fec51..a0144c00 100644 --- a/compiler/custom/s8_corner.py +++ b/compiler/custom/s8_corner.py @@ -27,7 +27,7 @@ class s8_corner(design.design): elif location == "ll": self.name = "s8sram16x16_cornera" elif location == "lr": - self.name = "s8sram16x16_cornerb" + self.name = "s8sram16x16_cornera" else: debug.error("Invalid s8_corner location", -1) design.design.__init__(self, name=self.name) diff --git a/compiler/custom/s8_replica_bitcell.py b/compiler/custom/s8_replica_bitcell.py index dd8fae0c..25965d9e 100644 --- a/compiler/custom/s8_replica_bitcell.py +++ b/compiler/custom/s8_replica_bitcell.py @@ -33,14 +33,26 @@ class replica_bitcell(design.design): type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: - (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"]) + (self.width, self.height) = utils.get_libcell_size(self.name, + GDS["unit"], + layer["mem"], + "s8sram_cell\x00") + self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"]) else: (width,height) = (0,0) pin_map = [] - def __init__(self, name=""): + def __init__(self, version, name=""): # Ignore the name argument + + if version == "opt1": + self.name = "s8sram_cell_opt1" + self.border_structure = "s8sram_cell" + elif version == "opt1a": + self.name = "s8sram_cell_opt1a" + self.border_structure = "s8sram_cell" + + self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"]) design.design.__init__(self, "replica_cell_6t") debug.info(2, "Create replica bitcell object") diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 9f908bbe..29bcb57a 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -58,9 +58,6 @@ class bitcell_array(bitcell_base_array): self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap")) self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p")) - - - def create_instances(self): """ Create the module instances used in this design """ diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 9004994b..bb4f72a2 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -5,6 +5,8 @@ # from bitcell_base_array import bitcell_base_array from sram_factory import factory +from tech import GDS,layer,drc,parameter,cell_properties +from tech import cell_properties as props from globals import OPTS @@ -38,21 +40,33 @@ class dummy_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) + + if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement): + self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) + self.cell = factory.create(module_type="bitcell") + else: + self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1") + self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a") + self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap")) + self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p")) + self.cell = factory.create(module_type="s8_bitcell", version = "opt1") + self.add_mod(self.dummy_cell2) self.add_mod(self.dummy_cell) - - self.cell = factory.create(module_type="bitcell") def create_instances(self): """ Create the module instances used in this design """ self.cell_inst = {} - for col in range(self.column_size): - for row in range(self.row_size): - name = "bit_r{0}_c{1}".format(row, col) - self.cell_inst[row, col]=self.add_inst(name=name, - mod=self.dummy_cell) - self.connect_inst(self.get_bitcell_pins(row, col)) - + if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement): + for col in range(self.column_size): + for row in range(self.row_size): + name = "bit_r{0}_c{1}".format(row, col) + self.cell_inst[row, col]=self.add_inst(name=name, + mod=self.dummy_cell) + self.connect_inst(self.get_bitcell_pins(row, col)) + else: + from tech import custom_cell_arrangement + custom_cell_arrangement(self) + def input_load(self): wl_wire = self.gen_wl_wire() return wl_wire.return_input_cap() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index d3c25ba0..e98a51dc 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -45,15 +45,11 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): debug.check(sum(rbl) <= len(self.all_ports), "Invalid number of RBLs for port configuration.") - if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): - # Two dummy rows plus replica even if we don't add the column - self.extra_rows = 2 + sum(rbl) - # Two dummy cols plus replica if we add the column - self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl - else: - self.extra_rows = 0 - self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl + # Two dummy rows plus replica even if we don't add the column + self.extra_rows = 2 + sum(rbl) + # Two dummy cols plus replica if we add the column + self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -123,15 +119,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): end_caps_enabled = cell_properties.bitcell.end_caps except AttributeError: end_caps_enabled = False - if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): # Dummy row - self.dummy_row = factory.create(module_type="dummy_array", + self.dummy_row = factory.create(module_type="dummy_array", cols=self.column_size, rows=1, # dummy column + left replica column column_offset=1 + self.add_left_rbl, mirror=0) - self.add_mod(self.dummy_row) + self.add_mod(self.dummy_row) + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): # Dummy Row or Col Cap, depending on bitcell array properties col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array") @@ -164,6 +160,25 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): mirror=(self.left_rbl + 1) %2) self.add_mod(self.row_cap_right) else: + # Dummy Row or Col Cap, depending on bitcell array properties + col_cap_module_type = ("s8_col_cap_array" if end_caps_enabled else "dummy_array") + self.col_cap_top = factory.create(module_type=col_cap_module_type, + cols=self.column_size, + rows=1, + # dummy column + left replica column(s) + column_offset=1 + self.add_left_rbl, + mirror=0, + location="top") + self.add_mod(self.col_cap_top) + + self.col_cap_bottom = factory.create(module_type=col_cap_module_type, + cols=self.column_size, + rows=1, + # dummy column + left replica column(s) + column_offset=1 + self.add_left_rbl, + mirror=0, + location="bottom") + self.add_mod(self.col_cap_bottom) # Dummy Col or Row Cap, depending on bitcell array properties row_cap_module_type = ("s8_row_cap_array" if end_caps_enabled else "dummy_array") @@ -258,8 +273,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): self.all_dummy_row_wordline_names = [x for sl in self.dummy_row_wordline_names for x in sl] for port in range(self.left_rbl + self.right_rbl): - wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports] - self.rbl_wordline_names.append(wordline_names) + if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): + wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports] + self.rbl_wordline_names.append(wordline_names) + else: + for x in self.all_ports: + wordline_names = [] + wordline_names.append("rbl_wl0_{0}_{1}".format(x, port)) + wordline_names.append("rbl_wl1_{0}_{1}".format(x, port)) + self.rbl_wordline_names.append(wordline_names) self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl] for port in self.all_ports: @@ -290,8 +312,11 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): def create_instances(self): """ Create the module instances used in this design """ - - supplies = ["vdd", "gnd"] + + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + self.supplies = ["vdd", "gnd"] + else: + self.supplies = ["vpwr", "vgnd"] # Used for names/dimensions only if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): @@ -302,52 +327,82 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Main array self.bitcell_array_inst=self.add_inst(name="bitcell_array", mod=self.bitcell_array) - self.connect_inst(self.all_bitline_names + self.all_wordline_names + supplies) + self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies) # Replica columns self.replica_col_insts = [] for port in range(self.add_left_rbl + self.add_right_rbl): self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), mod=self.replica_columns[port])) - self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies) - + self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies) # Dummy rows under the bitcell array (connected with with the replica cell wl) self.dummy_row_replica_insts = [] # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! for port in range(self.left_rbl + self.right_rbl): self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), - mod=self.dummy_row)) - self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + supplies) + mod=self.dummy_row)) + self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies) - # Top/bottom dummy rows or col caps - self.dummy_row_insts = [] - self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", - mod=self.col_cap)) - self.connect_inst(self.all_bitline_names - + self.dummy_row_wordline_names[0] - + supplies) - self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", - mod=self.col_cap)) - self.connect_inst(self.all_bitline_names - + self.dummy_row_wordline_names[1] - + supplies) - # Left/right Dummy columns - self.dummy_col_insts = [] - self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", - mod=self.row_cap_left)) - self.connect_inst(self.dummy_col_bitline_names[0] + self.replica_array_wordline_names + supplies) - self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", - mod=self.row_cap_right)) - self.connect_inst(self.dummy_col_bitline_names[1] + self.replica_array_wordline_names + supplies) + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + # Top/bottom dummy rows or col caps + self.dummy_row_insts = [] + self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", + mod=self.col_cap)) + self.connect_inst(self.all_bitline_names + + self.dummy_row_wordline_names[0] + + self.supplies) + self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", + mod=self.col_cap)) + self.connect_inst(self.all_bitline_names + + self.dummy_row_wordline_names[1] + + self.supplies) + # Left/right Dummy columns + self.dummy_col_insts = [] + self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", + mod=self.row_cap_left)) + self.connect_inst(self.dummy_col_bitline_names[0] + self.replica_array_wordline_names + self.supplies) + self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", + mod=self.row_cap_right)) + self.connect_inst(self.dummy_col_bitline_names[1] + self.replica_array_wordline_names + self.supplies) + else: + # Top/bottom dummy rows or col caps + self.dummy_row_insts = [] + self.dummy_row_insts.append(self.add_inst(name="col_cap_bottom", + mod=self.col_cap_bottom)) + self.connect_inst(self.all_bitline_names + + self.supplies) + self.dummy_row_insts.append(self.add_inst(name="col_cap_top", + mod=self.col_cap_top)) + self.connect_inst(self.all_bitline_names + + self.supplies) + # Left/right Dummy columns + self.dummy_col_insts = [] + self.dummy_col_insts.append(self.add_inst(name="row_cap_left", + mod=self.row_cap_left)) + self.connect_inst(self.replica_array_wordline_names + self.supplies) + self.dummy_col_insts.append(self.add_inst(name="row_cap_right", + mod=self.row_cap_right)) + self.connect_inst(self.replica_array_wordline_names + self.supplies) def create_layout(self): - - self.height = (self.row_size + self.extra_rows) * self.dummy_row.height - self.width = (self.column_size + self.extra_cols) * self.cell.width + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + self.height = (self.row_size + self.extra_rows) * self.dummy_row.height + self.width = (self.column_size + self.extra_cols) * self.cell.width + else: + self.width = self.row_cap_left.top_corner.width + self.row_cap_right.top_corner.width + (self.col_cap_top.colend1.width + self.col_cap_top.colend2.width) * (self.column_size + self.extra_cols) - self.col_cap_top.colend2.width + self.height = self.row_cap_left.height # This is a bitcell x bitcell offset to scale self.bitcell_offset = vector(self.cell.width, self.cell.height) + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + self.strap_offset = vector(0, 0) + self.col_end_offset = vector(self.cell.width, self.cell.height) + self.row_end_offset = vector(self.cell.width, self.cell.height) + else: + self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height) + self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height) + self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height) # Everything is computed with the main array at (0, 0) to start self.bitcell_array_inst.place(offset=[0, 0]) @@ -368,14 +423,23 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): def add_replica_columns(self): """ Add replica columns on left and right of array """ + end_caps_enabled = cell_properties.bitcell.end_caps # Grow from left to right, toward the array for bit in range(self.add_left_rbl): - offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1) + if not end_caps_enabled: + offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1) + self.strap_offset.scale(-self.add_left_rbl + bit, 0) + else: + offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(-self.add_left_rbl + bit, 0) + self.replica_col_insts[bit].place(offset) # Grow to the right of the bitcell array, array outward for bit in range(self.add_right_rbl): - offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1) + if not end_caps_enabled: + offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1) + self.strap_offset.scale(bit, -self.left_rbl - 1) + else: + offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.left_rbl - 1) + self.replica_col_insts[self.add_left_rbl + bit].place(offset) # Replica dummy rows @@ -391,26 +455,42 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): def add_end_caps(self): """ Add dummy cells or end caps around the array """ + end_caps_enabled = cell_properties.bitcell.end_caps # FIXME: These depend on the array size itself # Far top dummy row (first row above array is NOT flipped) flip_dummy = self.right_rbl % 2 - dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul() + if not end_caps_enabled: + dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul() + else: + dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul() + self.dummy_row_insts[1].place(offset=dummy_row_offset, mirror="MX" if flip_dummy else "R0") # FIXME: These depend on the array size itself # Far bottom dummy row (first row below array IS flipped) flip_dummy = (self.left_rbl + 1) % 2 - dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy) + if not end_caps_enabled: + dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy) + else: + dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - (self.col_end_offset.y/self.cell.height) + flip_dummy) self.dummy_row_insts[0].place(offset=dummy_row_offset, mirror="MX" if flip_dummy else "R0") # Far left dummy col # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array - dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1) + if not end_caps_enabled: + dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1) + else: + dummy_col_offset = self.bitcell_offset.scale(-(self.add_left_rbl*(1+self.strap_offset.x/self.cell.width)) - (self.row_end_offset.x/self.cell.width), -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.dummy_col_insts[0].place(offset=dummy_col_offset) # Far right dummy col # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array - dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl, -self.left_rbl - 1) + self.bitcell_array_inst.lr() + if not end_caps_enabled: + dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl*(1+self.strap_offset.x/self.cell.width), -self.left_rbl - 1) + self.bitcell_array_inst.lr() + else: + dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl*(1+self.strap_offset.x/self.cell.width), -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.bitcell_array_inst.lr() + self.dummy_col_insts[1].place(offset=dummy_col_offset) def add_layout_pins(self): @@ -470,7 +550,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # vdd/gnd are only connected in the perimeter cells # replica column should only have a vdd/gnd in the dummy cell on top/bottom supply_insts = self.dummy_col_insts + self.dummy_row_insts - for pin_name in ["vdd", "gnd"]: + + for pin_name in self.supplies: for inst in supply_insts: pin_list = inst.get_pins(pin_name) for pin in pin_list: diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index a28aebf9..a995c850 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -28,7 +28,10 @@ class replica_column(design.design): self.right_rbl = rbl[1] self.replica_bit = replica_bit # left, right, regular rows plus top/bottom dummy cells - self.total_size = self.left_rbl + rows + self.right_rbl + 2 + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + self.total_size = self.left_rbl + rows + self.right_rbl + 2 + else: + self.total_size = self.left_rbl + rows + self.right_rbl + 2 self.column_offset = column_offset debug.check(replica_bit != 0 and replica_bit != rows, @@ -78,13 +81,14 @@ class replica_column(design.design): self.add_pin_list(self.all_wordline_names, "INPUT") else: self.wordline_names = [[] for port in self.all_ports] - for row in range(self.rows): + for row in range(self.total_size): for port in self.all_ports: if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) else: - self.wordline_names[port].append("wl0_{0}_{1}".format(port, row)) - self.wordline_names[port].append("wl1_{0}_{1}".format(port, row)) + if (row > 0 and row < self.total_size-1): + self.wordline_names[port].append("wl0_{0}_{1}".format(port, row)) + self.wordline_names[port].append("wl1_{0}_{1}".format(port, row)) self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] self.add_pin_list(self.all_wordline_names, "INPUT") @@ -276,13 +280,13 @@ class replica_column(design.design): width=self.width, height=wl_pin.height()) - # # Supplies are only connected in the ends - # for (index, inst) in self.cell_inst.items(): - # for pin_name in ["vdd", "gnd"]: - # if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]: - # self.copy_power_pins(inst, pin_name) - # else: - # self.copy_layout_pin(inst, pin_name) + # Supplies are only connected in the ends + for (index, inst) in self.cell_inst.items(): + for pin_name in ["vpwr", "vgnd"]: + if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]: + self.copy_power_pins(inst, pin_name) + else: + self.copy_layout_pin(inst, pin_name) def get_bitline_names(self, port=None): if port == None: diff --git a/compiler/tests/sram_1b_16_1rw_sky130.log b/compiler/tests/sram_1b_16_1rw_sky130.log index f7fb9395..4fd3c1ee 100644 --- a/compiler/tests/sram_1b_16_1rw_sky130.log +++ b/compiler/tests/sram_1b_16_1rw_sky130.log @@ -1,9 +1,1761 @@ -ERROR: file hierarchy_spice.py: line 176: Connection mismatch: -Inst (4) -> Mod (6) -bl_0_0 -> bl0 -br_0_0 -> bl1 -vdd -> wl0 -gnd -> wl1 - -> vpwr - -> vgnd +[globals/init_openram]: Initializing OpenRAM... +[globals/setup_paths]: Temporary files saved in /home/jesse/output/ +[globals/read_config]: Configuration file is /home/jesse/openram/compiler/tests/configs/config.py +[globals/read_config]: Output saved in /home/jesse/openram/compiler/tests/./ +[globals/import_tech]: Adding technology path: /home/jesse/openram/technology +[globals/init_paths]: Creating temp directory: /home/jesse/output/ +[characterizer/]: Initializing characterizer... +[characterizer/]: Analytical model enabled. +[verify/]: Initializing verify... +[verify/]: Finding DRC/LVS/PEX tools. +[globals/get_tool]: Using DRC: /usr/local/bin/magic +[globals/get_tool]: Using LVS: /usr/local/bin/netgen +[globals/get_tool]: Using PEX: /usr/local/bin/magic +[globals/get_tool]: Using GDS: /usr/local/bin/magic +[bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4 +[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 +[bitcell_base_array/__init__]: Creating bitcell_array 4 x 4 +[bitcell_base_array/__init__]: Creating dummy_array 1 x 4 +[verify.magic/run_drc]: Cell replica_bitcell_array has 2074 error tiles. +WARNING: file magic.py: line 210: DRC Errors replica_bitcell_array 2074 + +[verify.magic/run_lvs]: Flattening unmatched subcell s8sram_cell in circuit s8sram_cell_opt1_ce (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8sram16x16_colend_ce in circuit s8sram16x16_colenda (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8sram_cell_opt1_ce in circuit s8sram_cell_opt1a (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8sram_cell_opt1_ce in circuit s8sram_cell_opt1 (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8_col_cap_array in circuit replica_bitcell_array (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8_row_cap_array in circuit replica_bitcell_array (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8_row_cap_array_0 in circuit replica_bitcell_array (0)(1 instance) +[verify.magic/run_lvs]: Flattening unmatched subcell s8_col_cap_array_0 in circuit replica_bitcell_array (0)(1 instance) +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: s8sram_colend_met2_0/m2_0_4# +[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: s8sram_colend_met2_0/m2_0_236# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: bl0 +[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: bl1 +[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: vpwr +[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: vgnd +[verify.magic/run_lvs]: Equate pins: cell s8sram16x16_colenda and/or s8sram16x16_colenda has no elements. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: s8sram_cell_met2_0/m2_0_59# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: bl0 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: bl1 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: wl0 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: wl1 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: vpwr +[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: vgnd +[verify.magic/run_lvs]: Equate pins: cell s8sram_cell_opt1a and/or s8sram_cell_opt1a has no elements. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: s8sram_cell_met2_0/m2_0_59# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: bl0 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: bl1 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: wl0 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: wl1 +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: vpwr +[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: vgnd +[verify.magic/run_lvs]: Equate pins: cell s8sram_cell_opt1 and/or s8sram_cell_opt1 has no elements. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell dummy_array disconnected node: vpwr +[verify.magic/run_lvs]: Cell dummy_array disconnected node: vgnd +[verify.magic/run_lvs]: Class dummy_array: Merged 1 devices. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# +[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell dummy_array disconnected node: vpwr +[verify.magic/run_lvs]: Cell dummy_array disconnected node: vgnd +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Subcircuit summary: +[verify.magic/run_lvs]: Circuit 1: dummy_array |Circuit 2: dummy_array +[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- +[verify.magic/run_lvs]: s8sram_cell_opt1a (4) |s8sram_cell_opt1a (4) +[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) +[verify.magic/run_lvs]: Number of devices: 6 **Mismatch** |Number of devices: 4 **Mismatch** +[verify.magic/run_lvs]: Number of nets: 20 **Mismatch** |Number of nets: 15 **Mismatch** +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): +[verify.magic/run_lvs]: Circuit 1: dummy_array |Circuit 2: dummy_array +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: bl0_0_3 |Net: col_0_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl0_0_2 |Net: col_1_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl0_0_1 |Net: col_2_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl0_0_0 |Net: col_3_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_3 |Net: bl_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_2 |Net: bl_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_1 |Net: bl_0_2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_0 |Net: bl_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_1674_61# |Net: br_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_1174_61# |Net: br_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_674_61# |Net: br_0_2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_62# |Net: br_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_1538_220# |Net: wl0_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/wl1 = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_1038_220# |Net: wl1_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/vpwr = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_538_220# |Net: vdd +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/vgnd = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_220# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: vpwr |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 4 | +[verify.magic/run_lvs]: s8sram_wlstrap/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_0/vpb |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 4 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: VSUBS |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 4 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl0_0_0 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): +[verify.magic/run_lvs]: Circuit 1: dummy_array |Circuit 2: dummy_array +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_wlstrap_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 10 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram16x16_wlstrap_p_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 10 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_3 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 +[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 4 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_2 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 +[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 4 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_1 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 +[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 4 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_0 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 +[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 4 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Netlists do not match. +[verify.magic/run_lvs]: Flattening non-matched subcircuits dummy_array dummy_array +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vpwr +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vgnd +[verify.magic/run_lvs]: Class bitcell_array: Merged 10 devices. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vpwr +[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vgnd +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Subcircuit summary: +[verify.magic/run_lvs]: Circuit 1: bitcell_array |Circuit 2: bitcell_array +[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- +[verify.magic/run_lvs]: s8sram_cell_opt1a (8) |s8sram_cell_opt1a (8) +[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1 (8) |s8sram_cell_opt1 (8) +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) +[verify.magic/run_lvs]: Number of devices: 18 **Mismatch** |Number of devices: 16 **Mismatch** +[verify.magic/run_lvs]: Number of nets: 43 **Mismatch** |Number of nets: 21 **Mismatch** +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): +[verify.magic/run_lvs]: Circuit 1: bitcell_array |Circuit 2: bitcell_array +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: bl1_0_3 |Net: vdd +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/vgnd = 8 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/vgnd = 8 +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_2 |Net: col_0_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_1 |Net: col_1_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: bl1_0_0 |Net: col_2_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: vpwr |Net: col_3_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 8 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 8 | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: s8sram_wlstrap/1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vgnd = 8 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vpwr = 8 | +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/vpb |Net: bl_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 8 | s8sram_cell_opt1a/bl1 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/vpb = 8 | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: VSUBS |Net: bl_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 8 | s8sram_cell_opt1a/bl1 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/vnb = 8 | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_0/s8sram_cell_opt1_ |Net: bl_0_2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl1 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_1/s8sram_cell_opt1_ |Net: bl_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl1 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_2/s8sram_cell_opt1_ |Net: br_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_3/s8sram_cell_opt1_ |Net: br_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_4/s8sram_cell_opt1_ |Net: br_0_2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_5/s8sram_cell_opt1_ |Net: br_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_6/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_7/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_0/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_1/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_2/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_3/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_4/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_5/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_6/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_7/s8sram_cell_opt1_ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_1/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_2/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_3/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_4/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_5/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_6/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_7/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_1/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_2/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_3/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_4/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_5/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_6/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_7/s8sram_cell_opt1_c |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_1 +[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_1 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_2 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_0 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_2 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_0 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: wl0_0_1 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl0_0_3 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: wl0_0_0 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl0_0_2 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): +[verify.magic/run_lvs]: Circuit 1: bitcell_array |Circuit 2: bitcell_array +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_wlstrap_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 34 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram16x16_wlstrap_p_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 34 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_7 |Instance: s8sram_cell_opt1row_3, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_6 |Instance: s8sram_cell_opt1row_3, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_5 |Instance: s8sram_cell_opt1row_3, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_4 |Instance: s8sram_cell_opt1row_3, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_3 |Instance: s8sram_cell_opt1row_1, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_2 |Instance: s8sram_cell_opt1row_1, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_1 |Instance: s8sram_cell_opt1row_1, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_0 |Instance: s8sram_cell_opt1row_1, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_7 |Instance: s8sram_cell_opt1arow_2, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_6 |Instance: s8sram_cell_opt1arow_2, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_5 |Instance: s8sram_cell_opt1arow_2, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_4 |Instance: s8sram_cell_opt1arow_2, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_3 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_2 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_1 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_0 |Instance: s8sram_cell_opt1arow_0, +[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 +[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 +[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 +[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 +[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 12 | +[verify.magic/run_lvs]: vnb = 16 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Netlists do not match. +[verify.magic/run_lvs]: Flattening non-matched subcircuits bitcell_array bitcell_arrayClass replica_column: Merged 4 devices. +[verify.magic/run_lvs]: Class replica_column: Merged 1 devices. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Subcircuit summary: +[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column +[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- +[verify.magic/run_lvs]: s8sram_cell_opt1a (2) |s8sram_cell_opt1a (2) +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1 (3) |s8sram_cell_opt1 (3) +[verify.magic/run_lvs]: s8sram16x16_colenda (2) |s8sram16x16_colenda (1) **Mismatch** +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: Number of devices: 10 **Mismatch** |Number of devices: 6 **Mismatch** +[verify.magic/run_lvs]: Number of nets: 22 **Mismatch** |Number of nets: 14 **Mismatch** +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_column makes a better match +[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_column makes a better match +[verify.magic/run_lvs]: Making another compare attempt. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Subcircuit summary: +[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column +[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- +[verify.magic/run_lvs]: s8sram_cell_opt1a (2) |s8sram_cell_opt1a (2) +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1 (3) |s8sram_cell_opt1 (3) +[verify.magic/run_lvs]: nshort (2) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: Number of devices: 10 **Mismatch** |Number of devices: 5 **Mismatch** +[verify.magic/run_lvs]: Number of nets: 22 **Mismatch** |Number of nets: 14 **Mismatch** +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): +[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: br_0_0 |Net: wl0_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1/wl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 3 | +[verify.magic/run_lvs]: nshort/(drain|source) = 4 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: vgnd |Net: wl0_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 2 | s8sram_cell_opt1/wl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 2 | +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vgnd = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vpwr = 3 | +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/1 = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl_0_5 |Net: wl0_0_5 +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | s8sram_cell_opt1/wl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl_0_3 |Net: wl1_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | s8sram_cell_opt1/wl1 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl_0_1 |Net: wl1_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | s8sram_cell_opt1/wl1 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_1737# |Net: wl1_0_5 +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | s8sram_cell_opt1/wl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_1105# |Net: bl_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | s8sram_cell_opt1/bl0 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_473# |Net: br_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | s8sram_cell_opt1/bl1 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl1 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_1895# |Net: vdd +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | s8sram_cell_opt1/vpwr = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_1263# |Net: gnd +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | s8sram_cell_opt1/vgnd = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vgnd = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_631# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram16x16_colend_p_cent_0/vpb |(no matching net) +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/2 = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_4 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_2 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_4 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_2 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: s8sram16x16_colenda_1/s8sram16x16_col |(no matching net) +[verify.magic/run_lvs]: nshort/gate = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram16x16_colenda_0/s8sram16x16_col |(no matching net) +[verify.magic/run_lvs]: nshort/gate = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: a_38_947# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_1579# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: a_38_789# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: a_38_1421# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: wl_0_2 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl_0_4 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: VSUBS |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vnb = 3 | +[verify.magic/run_lvs]: nshort/bulk = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/vpb |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 2 | +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/3 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vpb = 3 | +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/3 = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): +[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram16x16_colenda_p_cent_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 13 | +[verify.magic/run_lvs]: 2 = 2 | +[verify.magic/run_lvs]: 3 = 7 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram16x16_wlstrap_p_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 13 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram16x16_colend_p_cent_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 13 | +[verify.magic/run_lvs]: 2 = 2 | +[verify.magic/run_lvs]: 3 = 7 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram16x16_colenda_1//s8sram16x |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (14,14) | +[verify.magic/run_lvs]: gate = 1 | +[verify.magic/run_lvs]: bulk = 7 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram16x16_colenda_0//s8sram16x |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (14,14) | +[verify.magic/run_lvs]: gate = 1 | +[verify.magic/run_lvs]: bulk = 7 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_2 |Instance: s8sram_cell_opt1rbc_5 +[verify.magic/run_lvs]: bl0 = 14 | bl0 = 5 +[verify.magic/run_lvs]: bl1 = 14 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 13 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 13 | wl1 = 1 +[verify.magic/run_lvs]: vpb = 7 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 3 | vgnd = 5 +[verify.magic/run_lvs]: wl0 = 3 | +[verify.magic/run_lvs]: vnb = 7 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_1 |Instance: s8sram_cell_opt1rbc_3 +[verify.magic/run_lvs]: bl0 = 14 | bl0 = 5 +[verify.magic/run_lvs]: bl1 = 14 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 13 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 13 | wl1 = 1 +[verify.magic/run_lvs]: vpb = 7 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 3 | vgnd = 5 +[verify.magic/run_lvs]: wl0 = 3 | +[verify.magic/run_lvs]: vnb = 7 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_0 |Instance: s8sram_cell_opt1rbc_1 +[verify.magic/run_lvs]: bl0 = 14 | bl0 = 5 +[verify.magic/run_lvs]: bl1 = 14 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 13 | wl0 = 1 +[verify.magic/run_lvs]: vpwr = 13 | wl1 = 1 +[verify.magic/run_lvs]: vpb = 7 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 3 | vgnd = 5 +[verify.magic/run_lvs]: wl0 = 3 | +[verify.magic/run_lvs]: vnb = 7 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_0 |(no matching instance) +[verify.magic/run_lvs]: bl0 = 14 | +[verify.magic/run_lvs]: bl1 = 14 | +[verify.magic/run_lvs]: vgnd = 13 | +[verify.magic/run_lvs]: vpwr = 13 | +[verify.magic/run_lvs]: vpb = 7 | +[verify.magic/run_lvs]: wl1 = 3 | +[verify.magic/run_lvs]: wl0 = 3 | +[verify.magic/run_lvs]: vnb = 7 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_1 |(no matching instance) +[verify.magic/run_lvs]: bl0 = 14 | +[verify.magic/run_lvs]: bl1 = 14 | +[verify.magic/run_lvs]: vgnd = 13 | +[verify.magic/run_lvs]: vpwr = 13 | +[verify.magic/run_lvs]: vpb = 7 | +[verify.magic/run_lvs]: wl1 = 3 | +[verify.magic/run_lvs]: wl0 = 3 | +[verify.magic/run_lvs]: vnb = 7 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching instance) |Instance: s8sram_cell_opt1arbc_2 +[verify.magic/run_lvs]: | bl0 = 5 +[verify.magic/run_lvs]: | bl1 = 5 +[verify.magic/run_lvs]: | wl0 = 1 +[verify.magic/run_lvs]: | wl1 = 1 +[verify.magic/run_lvs]: | vpwr = 5 +[verify.magic/run_lvs]: | vgnd = 5 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching instance) |Instance: s8sram_cell_opt1arbc_4 +[verify.magic/run_lvs]: | bl0 = 5 +[verify.magic/run_lvs]: | bl1 = 5 +[verify.magic/run_lvs]: | wl0 = 1 +[verify.magic/run_lvs]: | wl1 = 1 +[verify.magic/run_lvs]: | vpwr = 5 +[verify.magic/run_lvs]: | vgnd = 5 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Netlists do not match. +[verify.magic/run_lvs]: Flattening non-matched subcircuits replica_column replica_column +[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: vdd +[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: gnd +[verify.magic/run_lvs]: Class replica_bitcell_array: Merged 23 devices. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: vdd +[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: gnd +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Subcircuit summary: +[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array +[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- +[verify.magic/run_lvs]: s8sram16x16_colenda (4) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1a (14) |s8sram_cell_opt1a (14) +[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1 (11) |s8sram_cell_opt1 (11) +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: nshort (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_corner (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_cornera (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_rowenda (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_rowend (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_cornerb (1) |(no matching element) +[verify.magic/run_lvs]: Number of devices: 39 **Mismatch** |Number of devices: 25 **Mismatch** +[verify.magic/run_lvs]: Number of nets: 62 **Mismatch** |Number of nets: 32 **Mismatch** +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_bitcell_array makes a better match +[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_bitcell_array makes a better match +[verify.magic/run_lvs]: Making another compare attempt. +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: vdd +[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: gnd +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: Subcircuit summary: +[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array +[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- +[verify.magic/run_lvs]: nshort (5) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1a (14) |s8sram_cell_opt1a (14) +[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) +[verify.magic/run_lvs]: s8sram_cell_opt1 (11) |s8sram_cell_opt1 (11) +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_corner (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_cornera (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_rowenda (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_rowend (1) |(no matching element) +[verify.magic/run_lvs]: s8sram16x16_cornerb (1) |(no matching element) +[verify.magic/run_lvs]: Number of devices: 39 **Mismatch** |Number of devices: 25 **Mismatch** +[verify.magic/run_lvs]: Number of nets: 62 **Mismatch** |Number of nets: 32 **Mismatch** +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): +[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_2 |Net: dummy_arraydummy_row_0/col_0_bitcell +[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_3 |Net: dummy_arraydummy_row_0/col_1_bitcell +[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_0 |Net: dummy_arraydummy_row_0/col_2_bitcell +[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_1 |Net: dummy_arraydummy_row_0/col_3_bitcell +[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: rbl_bl_0_0 |Net: bl_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl1 = 3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 3 | +[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 3 | +[verify.magic/run_lvs]: nshort/(drain|source) = 2 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: VSUBS |Net: bl_0_1 +[verify.magic/run_lvs]: nshort/bulk = 5 | s8sram_cell_opt1a/bl1 = 3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 14 | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1/vnb = 11 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: rbl_wl1_0_0 |Net: bl_0_2 +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/1 = 1 | s8sram_cell_opt1a/bl1 = 3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 14 | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 14 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: s8sram_wlstrap/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vgnd = 11 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vpwr = 11 | +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: s8sram16x16_corner/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_cornera/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_rowenda/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_rowenda/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_rowend/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_rowend/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_cornerb/1 = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: dummy_array_0/s8sram_cell_opt1a_0/vpb |Net: bl_0_3 +[verify.magic/run_lvs]: nshort/gate = 5 | s8sram_cell_opt1a/bl1 = 3 +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/2 = 1 | s8sram_cell_opt1/bl1 = 2 +[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/3 = 1 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 14 | +[verify.magic/run_lvs]: s8sram_cell_opt1/vpb = 11 | +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/3 = 1 | +[verify.magic/run_lvs]: s8sram16x16_corner/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_corner/3 = 1 | +[verify.magic/run_lvs]: s8sram16x16_cornera/1 = 1 | +[verify.magic/run_lvs]: s8sram16x16_cornera/3 = 1 | +[verify.magic/run_lvs]: s8sram16x16_cornerb/2 = 1 | +[verify.magic/run_lvs]: s8sram16x16_cornerb/3 = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_1674_61# |Net: br_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_1174_61# |Net: br_0_1 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_674_61# |Net: br_0_2 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_38_62# |Net: br_0_3 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_0/ |Net: vpwr +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/vpwr = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_1/ |Net: vgnd +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/vgnd = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vgnd = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_2/ |Net: rbl_bl_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/bl0 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_3/ |Net: rbl_br_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/bl1 = 3 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl1 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_4/ |Net: rbl_wl0_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/wl0 = 1 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_5/ |Net: rbl_wl1_0_0 +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/wl1 = 1 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_6/ |Net: dummy_arraydummy_row_0/vdd +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/vgnd = 4 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_7/ |Net: /bitcell_array/col_0_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1421# |Net: /bitcell_array/col_1_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_789# |Net: /bitcell_array/col_2_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_1538_220# |Net: /bitcell_array/col_3_bitcell +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/bl0 = 2 +[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_1038_220# |Net: /bitcell_array/vdd +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/vgnd = 8 +[verify.magic/run_lvs]: | s8sram_cell_opt1/vgnd = 8 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_538_220# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /dummy_array_0/a_38_220# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_0/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_1/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_2/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_3/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_4/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_5/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_6/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_7/ |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1579# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_947# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_0/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_1/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_2/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_3/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_4/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_5/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_6/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_7/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1737# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1105# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_473# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_0/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_1/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_2/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_3/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_4/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_5/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_6/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_7/s |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1895# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1263# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: /replica_column_0/a_38_631# |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_1 +[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 1 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_3 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_1 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 1 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_2 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_0 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_2 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_0 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 +[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: wl1_0_1 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl1_0_3 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Net: wl1_0_0 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Net: wl1_0_2 |(no matching net) +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 5 | +[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): +[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (12,12) | +[verify.magic/run_lvs]: gate = 40 | +[verify.magic/run_lvs]: bulk = 30 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (12,12) | +[verify.magic/run_lvs]: gate = 40 | +[verify.magic/run_lvs]: bulk = 30 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (12,12) | +[verify.magic/run_lvs]: gate = 40 | +[verify.magic/run_lvs]: bulk = 30 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (12,12) | +[verify.magic/run_lvs]: gate = 40 | +[verify.magic/run_lvs]: bulk = 30 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram16x16_co |(no matching instance) +[verify.magic/run_lvs]: (drain,source) = (12,12) | +[verify.magic/run_lvs]: gate = 40 | +[verify.magic/run_lvs]: bulk = 30 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: 2 = 40 | +[verify.magic/run_lvs]: 3 = 40 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_wlstrap_0 |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram16x16_wlstr |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram16x16_co |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: 2 = 40 | +[verify.magic/run_lvs]: 3 = 40 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: 2 = 40 | +[verify.magic/run_lvs]: 3 = 40 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: 1 = 40 | +[verify.magic/run_lvs]: 2 = 76 | +[verify.magic/run_lvs]: 3 = 40 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: 2 = 76 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: 2 = 76 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: s8_row_cap_array_0_0//s8sram16x1 |(no matching instance) +[verify.magic/run_lvs]: 1 = 76 | +[verify.magic/run_lvs]: 2 = 40 | +[verify.magic/run_lvs]: 3 = 40 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: replica_columnreplica_col_0/s8sr +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 5 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 76 | vgnd = 5 +[verify.magic/run_lvs]: wl0 = 76 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |(no matching instance) +[verify.magic/run_lvs]: bl0 = 12 | +[verify.magic/run_lvs]: bl1 = 12 | +[verify.magic/run_lvs]: vgnd = 76 | +[verify.magic/run_lvs]: vpwr = 76 | +[verify.magic/run_lvs]: vpb = 40 | +[verify.magic/run_lvs]: wl1 = 15 | +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |(no matching instance) +[verify.magic/run_lvs]: bl0 = 12 | +[verify.magic/run_lvs]: bl1 = 12 | +[verify.magic/run_lvs]: vgnd = 76 | +[verify.magic/run_lvs]: vpwr = 76 | +[verify.magic/run_lvs]: vpb = 40 | +[verify.magic/run_lvs]: wl1 = 15 | +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr +[verify.magic/run_lvs]: | bl0 = 5 +[verify.magic/run_lvs]: | bl1 = 5 +[verify.magic/run_lvs]: | wl0 = 5 +[verify.magic/run_lvs]: | wl1 = 5 +[verify.magic/run_lvs]: | vpwr = 5 +[verify.magic/run_lvs]: | vgnd = 5 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr +[verify.magic/run_lvs]: | bl0 = 5 +[verify.magic/run_lvs]: | bl1 = 5 +[verify.magic/run_lvs]: | wl0 = 5 +[verify.magic/run_lvs]: | wl1 = 5 +[verify.magic/run_lvs]: | vpwr = 5 +[verify.magic/run_lvs]: | vgnd = 5 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: dummy_arraydummy_row_0/s8sram_ce +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: dummy_arraydummy_row_0/s8sram_ce +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: dummy_arraydummy_row_0/s8sram_ce +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: dummy_arraydummy_row_0/s8sram_ce +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 15 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 76 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 76 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |Instance: bitcell_array/s8sram_cell_opt1ar +[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 +[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 +[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 +[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 +[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 +[verify.magic/run_lvs]: wl1 = 76 | vgnd = 16 +[verify.magic/run_lvs]: wl0 = 76 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |(no matching instance) +[verify.magic/run_lvs]: bl0 = 12 | +[verify.magic/run_lvs]: bl1 = 12 | +[verify.magic/run_lvs]: vgnd = 76 | +[verify.magic/run_lvs]: vpwr = 76 | +[verify.magic/run_lvs]: vpb = 40 | +[verify.magic/run_lvs]: wl1 = 76 | +[verify.magic/run_lvs]: wl0 = 76 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |(no matching instance) +[verify.magic/run_lvs]: bl0 = 12 | +[verify.magic/run_lvs]: bl1 = 12 | +[verify.magic/run_lvs]: vgnd = 76 | +[verify.magic/run_lvs]: vpwr = 76 | +[verify.magic/run_lvs]: vpb = 40 | +[verify.magic/run_lvs]: wl1 = 76 | +[verify.magic/run_lvs]: wl0 = 76 | +[verify.magic/run_lvs]: vnb = 30 | +[verify.magic/run_lvs]: a_38_62# = 1 | +[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | +[verify.magic/run_lvs]: a_38_220# = 1 | +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr +[verify.magic/run_lvs]: | bl0 = 5 +[verify.magic/run_lvs]: | bl1 = 5 +[verify.magic/run_lvs]: | wl0 = 5 +[verify.magic/run_lvs]: | wl1 = 5 +[verify.magic/run_lvs]: | vpwr = 5 +[verify.magic/run_lvs]: | vgnd = 5 +[verify.magic/run_lvs]: | +[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr +[verify.magic/run_lvs]: | bl0 = 5 +[verify.magic/run_lvs]: | bl1 = 5 +[verify.magic/run_lvs]: | wl0 = 5 +[verify.magic/run_lvs]: | wl1 = 5 +[verify.magic/run_lvs]: | vpwr = 5 +[verify.magic/run_lvs]: | vgnd = 5 +[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- +[verify.magic/run_lvs]: Netlists do not match. +[verify.magic/run_lvs]: Netlists do not match. +ERROR: file magic.py: line 285: replica_bitcell_array LVS mismatch (results in /home/jesse/output/replica_bitcell_array.lvs.report) diff --git a/missing_pin.gds b/missing_pin.gds index 25df96f6..0bad623f 100644 Binary files a/missing_pin.gds and b/missing_pin.gds differ diff --git a/sram_1b_16_1rw_sky130.log b/sram_1b_16_1rw_sky130.log index 18538d57..9b298b1e 100644 --- a/sram_1b_16_1rw_sky130.log +++ b/sram_1b_16_1rw_sky130.log @@ -15,12 +15,4 @@ [bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4 [replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 [bitcell_base_array/__init__]: Creating bitcell_array 4 x 4 -ERROR: file hierarchy_spice.py: line 176: Connection mismatch: -Inst (4) -> Mod (6) -bl_0_0 -> bl0 -br_0_0 -> bl1 -vdd -> wl0 -gnd -> wl1 - -> vpwr - -> vgnd - +[bitcell_base_array/__init__]: Creating dummy_array 1 x 4