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sky130 rba done

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This commit is contained in:
jcirimel
2020-09-30 07:34:05 -07:00
parent 3dd72cdeac
commit 7cbf456a4f
10 changed files with 1949 additions and 97 deletions
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compiler/custom/s8_col_end.py
+2 -2
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@@ -21,8 +21,8 @@ class s8_col_end(design.design):
type_list = []
if version == "colend":
self.name = "s8sram16x16_colend"
structure = "s8sram16x16_colend\x00"
self.name = "s8sram16x16_colenda"
structure = "s8sram16x16_colenda\x00"
elif version == "colend_p_cent":
self.name = "s8sram16x16_colend_p_cent"
structure = "s8sram16x16_colend_p_cent\x00"
compiler/custom/s8_corner.py
+1 -1
View File
@@ -27,7 +27,7 @@ class s8_corner(design.design):
elif location == "ll":
self.name = "s8sram16x16_cornera"
elif location == "lr":
self.name = "s8sram16x16_cornerb"
self.name = "s8sram16x16_cornera"
else:
debug.error("Invalid s8_corner location", -1)
design.design.__init__(self, name=self.name)
compiler/custom/s8_replica_bitcell.py
+15 -3
View File
@@ -33,14 +33,26 @@ class replica_bitcell(design.design):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"])
(self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"],
layer["mem"],
"s8sram_cell\x00")
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, name=""):
def __init__(self, version, name=""):
# Ignore the name argument
if version == "opt1":
self.name = "s8sram_cell_opt1"
self.border_structure = "s8sram_cell"
elif version == "opt1a":
self.name = "s8sram_cell_opt1a"
self.border_structure = "s8sram_cell"
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
design.design.__init__(self, "replica_cell_6t")
debug.info(2, "Create replica bitcell object")