From 7cac1a03573840f941948e9c35d8a56f853cc4a8 Mon Sep 17 00:00:00 2001
From: mguthaus <mrg@ucsc.edu>
Date: Sat, 15 Apr 2017 07:49:05 -0700
Subject: [PATCH] Rename test classes.

---
 compiler/router/router.py                       |  7 ++++++-
 compiler/router/tests/02_blockages_test.py      |  2 +-
 .../router/tests/03_same_layer_pins_test.py     |  2 +-
 .../router/tests/04_diff_layer_pins_test.py     | 17 ++++-------------
 compiler/router/tests/05_two_nets_test.py       | 16 ++++++----------
 5 files changed, 18 insertions(+), 26 deletions(-)

diff --git a/compiler/router/router.py b/compiler/router/router.py
index 0eae2d5d..04e24111 100644
--- a/compiler/router/router.py
+++ b/compiler/router/router.py
@@ -118,12 +118,17 @@ class router:
         for layer in self.layers:
             self.write_obstacle(self.top_name)
 
-    def clear_pins(self):
+    def clear(self):
         """
         Reset the source and destination pins to start a new routing.
+        Convert the source/dest to blockages.
+        Keep the other blockages.
+        Clear other pins from blockages?
+        
         """
         self.source = []
         self.dest = []
+        
 
     def route(self, layers, src, dest):
         """ 
diff --git a/compiler/router/tests/02_blockages_test.py b/compiler/router/tests/02_blockages_test.py
index e4e5f6cf..f1fcc4d5 100644
--- a/compiler/router/tests/02_blockages_test.py
+++ b/compiler/router/tests/02_blockages_test.py
@@ -11,7 +11,7 @@ import debug
 import calibre
 
 
-class no_blockages_test(unittest.TestCase):
+class blockages_test(unittest.TestCase):
 
     def runTest(self):
         globals.init_openram("config_{0}".format(OPTS.tech_name))
diff --git a/compiler/router/tests/03_same_layer_pins_test.py b/compiler/router/tests/03_same_layer_pins_test.py
index 1dd81f49..f40965c6 100644
--- a/compiler/router/tests/03_same_layer_pins_test.py
+++ b/compiler/router/tests/03_same_layer_pins_test.py
@@ -11,7 +11,7 @@ import debug
 import calibre
 
 
-class no_blockages_test(unittest.TestCase):
+class same_layer_pins_test(unittest.TestCase):
 
     def runTest(self):
         globals.init_openram("config_{0}".format(OPTS.tech_name))
diff --git a/compiler/router/tests/04_diff_layer_pins_test.py b/compiler/router/tests/04_diff_layer_pins_test.py
index d5db9f09..6cfb7784 100644
--- a/compiler/router/tests/04_diff_layer_pins_test.py
+++ b/compiler/router/tests/04_diff_layer_pins_test.py
@@ -11,7 +11,7 @@ import debug
 import calibre
 
 
-class no_blockages_test(unittest.TestCase):
+class diff_layer_pins_test(unittest.TestCase):
 
     def runTest(self):
         globals.init_openram("config_{0}".format(OPTS.tech_name))
@@ -49,21 +49,12 @@ class no_blockages_test(unittest.TestCase):
                 self.gdsname = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),gdsname)
                 r=router.router(self.gdsname)
                 layer_stack =("metal1","via1","metal2")
-                (src_rect,path,dest_rect)=r.route(layer_stack,src="A",dest="B")
-                self.add_rect(layer=layer_stack[0],
-                              offset=src_rect[0],
-                              width=src_rect[1].x-src_rect[0].x,
-                              height=src_rect[1].y-src_rect[0].y)
-                self.add_wire(layer_stack,path)
-                self.add_rect(layer=layer_stack[0],
-                              offset=dest_rect[0],
-                              width=dest_rect[1].x-dest_rect[0].x,
-                              height=dest_rect[1].y-dest_rect[0].y)
-
+                r.route(layer_stack,src="A",dest="B")
+                r.add_route(self)
 
         
         
-        r = routing("test1", "AB_diff_layer_pins")
+        r = routing("test1", "04_diff_layer_pins_test")
         self.local_check(r)
         
         # fails if there are any DRC errors on any cells
diff --git a/compiler/router/tests/05_two_nets_test.py b/compiler/router/tests/05_two_nets_test.py
index cd58564c..f12c6d16 100644
--- a/compiler/router/tests/05_two_nets_test.py
+++ b/compiler/router/tests/05_two_nets_test.py
@@ -11,7 +11,7 @@ import debug
 import calibre
 
 
-class no_blockages_test(unittest.TestCase):
+class two_nets_test(unittest.TestCase):
 
     def runTest(self):
         globals.init_openram("config_{0}".format(OPTS.tech_name))
@@ -49,18 +49,14 @@ class no_blockages_test(unittest.TestCase):
                 self.gdsname = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),gdsname)
                 r=router.router(self.gdsname)
                 layer_stack =("metal1","via1","metal2")
-                path=r.route(layer_stack,src="A",dest="B")
-                self.add_wire(layer_stack,path)
+                r.route(layer_stack,src="A",dest="B")
+                r.add_route(self)
 
-                path=r.route(layer_stack,src="C",dest="D")
-                self.add_wire(layer_stack,path)
-                
-                r.rg.view()
-                
+                r.route(layer_stack,src="A",dest="B")
+                r.add_route(self)
 
         
-        
-        r = routing("test1", "ABCD_two_nets")
+        r = routing("test1", "05_two_nets_test")
         self.local_check(r)
         
         # fails if there are any DRC errors on any cells