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Fix missing port in control logic

This commit is contained in:
Matt Guthaus 2019-08-01 12:42:51 -07:00
parent 8771ffbfed
commit 7ba97ee0ba
1 changed files with 3 additions and 2 deletions
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5
compiler/modules/control_logic.py
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@ -345,11 +345,12 @@ class control_logic(design.design):
# Outputs to the bank # Outputs to the bank
if self.port_type == "rw": if self.port_type == "rw":
self.output_list = ["rbl_wl", "s_en", "w_en", "p_en_bar"] self.output_list = ["rbl_wl", "s_en", "w_en"]
elif self.port_type == "r": elif self.port_type == "r":
self.output_list = ["rbl_wl", "s_en", "p_en_bar"] self.output_list = ["rbl_wl", "s_en"]
else: else:
self.output_list = ["w_en"] self.output_list = ["w_en"]
self.output_list.append("p_en_bar")
self.output_list.append("wl_en") self.output_list.append("wl_en")
self.output_list.append("clk_buf") self.output_list.append("clk_buf")