From 7ba97ee0ba6c422d7d70acd2e97ec3035cd2be1d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 1 Aug 2019 12:42:51 -0700 Subject: [PATCH] Fix missing port in control logic --- compiler/modules/control_logic.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 2fbaf31c..8ae62401 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -345,11 +345,12 @@ class control_logic(design.design): # Outputs to the bank if self.port_type == "rw": - self.output_list = ["rbl_wl", "s_en", "w_en", "p_en_bar"] + self.output_list = ["rbl_wl", "s_en", "w_en"] elif self.port_type == "r": - self.output_list = ["rbl_wl", "s_en", "p_en_bar"] + self.output_list = ["rbl_wl", "s_en"] else: self.output_list = ["w_en"] + self.output_list.append("p_en_bar") self.output_list.append("wl_en") self.output_list.append("clk_buf")