From 766042fe6970ad3f9919966e9f698b0eb3934829 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Tue, 22 May 2018 14:16:51 -0700 Subject: [PATCH] changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit --- compiler/modules/bitcell.py | 36 ++++++++++----------- compiler/pgates/precharge.py | 8 ++--- compiler/pgates/single_level_column_mux.py | 4 +-- technology/scn3me_subm/gds_lib/cell_6t.gds | Bin 5916 -> 6144 bytes 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/compiler/modules/bitcell.py b/compiler/modules/bitcell.py index 473634f2..33707b81 100644 --- a/compiler/modules/bitcell.py +++ b/compiler/modules/bitcell.py @@ -11,7 +11,7 @@ class bitcell(design.design): library. """ - pin_names = ["BL", "BR", "WL", "vdd", "gnd"] + pin_names = ["bl", "br", "wl", "vdd", "gnd"] (width,height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"]) pin_map = utils.get_libcell_pins(pin_names, "cell_6t", GDS["unit"], layer["boundary"]) @@ -37,7 +37,7 @@ class bitcell(design.design): def list_bitcell_pins(self, col, row): - # Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array + """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ bitcell_pins = ["bl[{0}]".format(col), "br[{0}]".format(col), "wl[{0}]".format(row), @@ -47,44 +47,44 @@ class bitcell(design.design): def list_row_pins(self): - # Creates a list of row pins - row_pins = ["WL"] + """ Creates a list of all row pins (except for gnd and vdd) """ + row_pins = ["wl"] return row_pins def list_read_row_pins(self): - # Creates a list of row pins - row_pins = ["WL"] + """ Creates a list of row pins associated with read ports """ + row_pins = ["wl"] return row_pins def list_write_row_pins(self): - # Creates a list of row pins - row_pins = ["WL"] + """ Creates a list of row pins associated with write ports """ + row_pins = ["wl"] return row_pins def list_column_pins(self): - # Creates a list of column pins - column_pins = ["BL", "BR"] + """ Creates a list of all column pins (except for gnd and vdd) """ + column_pins = ["bl", "br"] return column_pins def list_read_column_pins(self): - # Creates a list of column pins - column_pins = ["BL"] + """ Creates a list of column pins associated with read ports """ + column_pins = ["bl"] return column_pins def list_read_bar_column_pins(self): - # Creates a list of column pins - column_pins = ["BR"] + """ Creates a list of column pins associated with read_bar ports """ + column_pins = ["br"] return column_pins def list_write_column_pins(self): - # Creates a list of column pins - column_pins = ["BL"] + """ Creates a list of column pins associated with write ports """ + column_pins = ["bl"] return column_pins def list_write_bar_column_pins(self): - # Creates a list of column pins - column_pins = ["BR"] + """ Creates a list of column pins asscociated with write_bar ports""" + column_pins = ["br"] return column_pins def analytical_power(self, proc, vdd, temp, load): diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 665bb710..c329efbe 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -81,12 +81,12 @@ class precharge(pgate.pgate): """Adds both the upper_pmos and lower_pmos to the module""" # adds the lower pmos to layout #base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0) - self.lower_pmos_position = vector(self.bitcell.get_pin("BL").lx(), + self.lower_pmos_position = vector(self.bitcell.get_pin("bl").lx(), self.pmos.active_offset.y) self.lower_pmos_inst=self.add_inst(name="lower_pmos", mod=self.pmos, offset=self.lower_pmos_position) - self.connect_inst(["bl", "en", "BR", "vdd"]) + self.connect_inst(["bl", "en", "br", "vdd"]) # adds the upper pmos(s) to layout ydiff = self.pmos.height + 2*self.m1_space + contact.poly.width @@ -158,7 +158,7 @@ class precharge(pgate.pgate): def add_bitlines(self): """Adds both bit-line and bit-line-bar to the module""" # adds the BL on metal 2 - offset = vector(self.bitcell.get_pin("BL").cx(),0) - vector(0.5 * self.m2_width,0) + offset = vector(self.bitcell.get_pin("bl").cx(),0) - vector(0.5 * self.m2_width,0) self.add_layout_pin(text="bl", layer="metal2", offset=offset, @@ -166,7 +166,7 @@ class precharge(pgate.pgate): height=self.height) # adds the BR on metal 2 - offset = vector(self.bitcell.get_pin("BR").cx(),0) - vector(0.5 * self.m2_width,0) + offset = vector(self.bitcell.get_pin("br").cx(),0) - vector(0.5 * self.m2_width,0) self.add_layout_pin(text="br", layer="metal2", offset=offset, diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 24f3b1fa..22dde391 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -39,8 +39,8 @@ class single_level_column_mux(design.design): def add_bitline_pins(self): """ Add the top and bottom pins to this cell """ - bl_pos = vector(self.bitcell.get_pin("BL").lx(), 0) - br_pos = vector(self.bitcell.get_pin("BR").lx(), 0) + bl_pos = vector(self.bitcell.get_pin("bl").lx(), 0) + br_pos = vector(self.bitcell.get_pin("br").lx(), 0) # bl and br self.add_layout_pin(text="bl", diff --git a/technology/scn3me_subm/gds_lib/cell_6t.gds b/technology/scn3me_subm/gds_lib/cell_6t.gds index c6fdb0e8208d82752b8df1f873200eaf17b8e3c1..ec9264568959cc70edee2dc6cb55ac528ede4993 100644 GIT binary patch literal 6144 zcmd6rJ&YAq6vxlL_jY)=&*kk3>@HaZf(ZKoEbJ+D^l^W4=FiNmo_WT~O_m?|-}9ey?#J9a zcP+D)Wi~s~vPo;(4x6x!_0#`HZQRDJXQ!;!%2qGE{l*7t@0)FJkG}BYrzc+e@vHmK zon1eA^UK%H*z9P7H_P6-w6^y8v&q}(nq`l-Y~Hf*mYFT~+k?UHH_i4va6bQo*|C#m zqV#3e0q-bysheADE(%$dk2F*zlLUG>t=g@5~b&C@OwP|9n)s> zOC@<;@!Zfqw(fa|<+p!Xl-`uT7L(`4PaXaowb#b4*8c-n&1Puz?`5WULz=Uewf>9ODQ9=zjZ?UP@Wo*3l!+KHo9eAFOHALb_>KjTGyQF>ySpKlKG zK;rp!5T(cYecTS-apGg#MCrr)a~=0nH~B^B>3P-qkCgN8=Ue-lbM&sCU!wH(waCx6 zr>}R&S@_heC3zo;_8`CS735>jU<{{kl$4$r`nxNhAMQMB_Sk17$zQZL`tcFR8sK|V zl%Ck=CmuhwvyY0>6GK0-`Xx7hQF>zNXOCr!A>&WYqV&W@Kk@ikugsq)Ju&oiUJwsi zclbr=iJ@QP23hyapGg0U_C`PP#F3ZtMwFgd^&c(QzrQbdd2h(goQcvCLqF#Obwa*@ zm^)GWrunPopWN`h4>I1=A+jeI?Roy5-~WzTwv+o`HZ{V(yZE=)Z~NYnYRzV{kJf4x zCx>o~^w8gSddk-_JEl{5&T5Zq{w-aP+tPI(HzoZ2%hH?t9y5B^$w>2+FG}C^#@F(* zQxN}8JBIYcuzp6DTLt9ngZ!fO#L&;|(r3tQF@B=-#6~~y_?ZLV98r2==&#;#iRaA~ z$zQaGepV&@zZrj#=M?Q>{j59UAvZ++FG^1g{p>WvL2jyyzbL)Quezab zx+4CfJ;?9lrkgc&Gk&797Nw`>Rr4RO?qAb4{MN(z^;@ne{cks}n!mf^ zaqRB+*)yEdoBhl&J2PYsIb}rYi9!9IWB(y1K5~oFW51sW+>9nS%(yA>E{W20W9s>d zu^gQk{I%!!DksL9?|H?;9DGw1j^d0N=3t+G=2z>^WFM}srbCLqL=N-t<&b`o=bd-| zttWSE@^l~dzdZjAT=libm}}iRrRS{9UmCyC{~ylJnx8$AcLtJ|^Fx%L80Kfc;eCVn z*#AW7o8F&V{_6RSkMqLm{V&>s{KV+jebkJiAjZC#{S8>rt#U<^C;c Lt)$oMfBf?h%e|6$ literal 5916 zcmbuDJ&cr96owD8v$G?tIJ@q`E?Hm=g6uE5>?-R|3>rGNFiIjZB$~KJ3SuY>p`@_T zgo1*?L<$NLEhsD~wy>ZuhLXatL*4ElH_cx7%WQR{=IcL(E_!=&%uN2det+~` z-4KbRxUly<^)J(9TeJ}DJIx0pS#jV=Y{EKz{!ZX)2o18KeSqthS zx?c3Z^ouX<_h#Z;Q*nc?XZ&Wnw!=q${2B*3L&6mqKo_zqPab@FZXk0&7YFz&;MqI zE_!>`zkf4)2XEEHhc4#*-R?g>NA4YqHOH=pF8bKA`I#qU=d2T%54u?Lk3P~EL^H<1 z{DVC`n}7di_zvC@!^iybSM3>pc-Uw36_@UWF1nua$DHvoS8?f1=wivg?{WATFMfy* zT`c*jGd}7s;zJkn{+K7Zn7^o+imqqpPab^a7nuXPIN)DS_fLC0ysS4dAn$E-(e*U{ zQ~s$NW;?H%iNsM{=z7-AzTv(7;+dM{MHdI&-+lR6cg{%sBJt2g*R%QQ$NhQFshY%5 z+^Rk6XU=@6waD4UchSFR{nUs11AY;2Rkt1o?hk$QrypY{mq;ANt=fzEx%aYuB5@QK z4%~nH@^i)wKZyB?oZsl8>)HI&p1iD|Nd3{peExW641E#r9dY_z=yt~u2W*yjv=;FZo_vI&Fx>l?mYk@9$dz%0F;P`p((O=}f$N0s8 z_g~_V^M`qJ{)mUKgf0%uKk>&ogO5EgQa8>YvE*;BN3NY$#TW}UVN6wfcK%a0!ng0S z7(Uhnf7PD)SL^!4bMo~4JM@i{Puh!q?mX%JdF`5fL2u9aVYnn{EU;e=A0CXg)X|DnSa!WzZIyTc;t5IqU#xdb8NbLp&_&m? ze#S{Z@{5cEU39(ZColJQkvNJAOZj=uSa)hAvVJ-{s`hMt-ZSalgSzRxBYJzrAI}-@ zE%J+;Mf@!y4!pmT^TTYU9evZkpLmu>+VMs(e=#uW6v;8o*xk(dq8wO>;HfC<2j4E z&98`&m*