mirror of https://github.com/VLSIDA/OpenRAM.git
249 lines
8.0 KiB
Python
249 lines
8.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from .bitcell_base_array import bitcell_base_array
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from base import vector
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from globals import OPTS
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from sram_factory import factory
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class rom_base_array(bitcell_base_array):
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def __init__(self, rows, cols, bitmap, name="", column_offset=0):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=column_offset)
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#TODO: data is input in col-major order for ease of parsing, create a function to convert a row-major input to col-major
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self.data = bitmap
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self.route_layer = 'm1'
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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#self.add_layout_pins()
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self.place_ptx()
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#self.route_horizontal_pins(insts=self.cell_inst.values(), layer=self.route_layer, name="S")
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#self.route_bitlines()
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#self.route_wordlines()
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self.route_supplies()
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self.add_boundary()
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#self.DRC_LVS()
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#def add_pins(self):
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def add_boundary(self):
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self.width = self.cell.width * self.column_size
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self.height = self.cell.height * self.row_size
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super().add_boundary()
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def add_modules(self):
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# base cell, nmos tx that represents a 1
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self.cell = factory.create(module_type="rom_base_cell")
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# "dummy" cells represent 0
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#dummy cell with no contacts
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self.dummy_nc = factory.create(module_type="rom_dummy_cell")
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#dummy cell with drain contact
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self.dummy_dc = factory.create(module_type="rom_dummy_cell", drain_contact=True)
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#dummy cell with source contact
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self.dummy_sc = factory.create(module_type="rom_dummy_cell", source_contact=True)
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#dummy cell with all contacts
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self.dummy_ac = factory.create(module_type="rom_dummy_cell", source_contact=True, drain_contact=True)
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def create_instances(self):
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self.cell_inst = {}
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self.cell_list = []
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self.current_row = 0
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for row in range(self.row_size):
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row_list = []
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for col in range(self.column_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if(self.data[row][col] == 1):
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(["vdd", "gnd", "gnd"])
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else:
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if col < self.column_size - 1 and col > 0 and self.data[row][col + 1] == 1 and self.data[row][col - 1] == 1:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_ac)
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elif col > 0 and self.data[row][col - 1] == 1:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_dc)
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elif col < self.column_size - 1 and self.data[row][col + 1] == 1:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_sc)
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else:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_nc)
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self.connect_inst([])
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row_list.append(self.cell_inst[row, col])
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self.cell_list.append(row_list)
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def create_all_bitline_names(self):
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for col in range(self.column_size):
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for port in self.all_ports:
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self.bitline_names[port].extend(["bl_{0}_{1}".format(port, col)])
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def place_ptx(self):
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self.cell_pos = {}
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# rows are bitlines
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for row in range(self.row_size):
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# columns are word lines
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for col in range(self.column_size):
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cell_x = (self.cell.width) * col
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cell_y = row * (self.cell.height)
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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#cell_x = self.cell.width * col
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#cell_y = self.cell.height * row
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#print(self.nmos.height + self.nmos.poly_extend_active)
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if(self.data[row][col] == 1):
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pass
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#self.add_label("S_{}_{}".format(row,col), self.route_layer, self.cell_inst[row, col].center())
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#self.add_label("D", self.route_layer, self.cell_inst[row, col].center())
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#else:
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#poly_offset = (self.nmos.contact_offset + vector(0.5 * self.nmos.active_contact.width + 0.5 * self.nmos.poly_width + self.nmos.active_contact_to_gate, 0)) + (0, cell_y)
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#poly_offset = (cell_x, cell_y)
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#print(cell_x,cell_y)
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#self.add_rect(layer="poly",
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# offset=poly_offset,
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# width=self.nmos.height + self.nmos.poly_extend_active,
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# height=self.nmos.poly_width
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# )
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def route_bitlines(self):
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#get first nmos in col
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#connect to main bitline wire
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#get next nmos in col
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#route source to drain
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#loop
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for col in range(self.column_size):
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for row in range(self.row_size ):
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#nmos at this position and another nmos further down
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if self.data[row][col] == 1 :
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next_row = self.get_next_cell_in_bl(row, col)
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if next_row != -1:
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drain_pin = self.cell_inst[row, col].get_pin("D")
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source_pin = self.cell_inst[next_row, col].get_pin("S")
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source_pos = source_pin.bc()
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drain_pos = drain_pin.bc()
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self.add_path(self.route_layer, [drain_pos, source_pos])
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def get_next_cell_in_bl(self, row_start, col):
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for row in range(row_start + 1, self.row_size):
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if self.data[row][col] == 1:
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return row
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return -1
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def get_current_bl_interconnect(self, col):
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"""Get interconnect net for bitline(col) currently being connected """
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return "bli_{0}_{1}".format(self.current_row, col)
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def create_next_bl_interconnect(self, row, col):
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"""create a new net name for a bitline interconnect"""
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self.current_row = row
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return "bli_{0}_{1}".format(row, col)
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def get_bitcell_pins(self, row, col):
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"""
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return the correct nets to attack nmos/cell drain, gate, source, body pins to
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"""
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bitcell_pins = []
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#drain pin
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if self.current_row == 0:
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bitcell_pins.append(self.bitline_names[0][col])
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else:
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bitcell_pins.append(self.get_current_bl_interconnect(col))
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#gate pin
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bitcell_pins.append(self.get_wordline_names()[row])
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#source pin
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"""If there is another bitcell to be placed below the current cell, """
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if self.get_next_cell_in_bl(row, col) == -1:
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bitcell_pins.append("gnd")
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else:
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"""create another interconnect net"""
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bitcell_pins.append(self.create_next_bl_interconnect(row, col))
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#body pin
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bitcell_pins.append("gnd")
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return bitcell_pins
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