mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-05 09:03:53 +02:00
Added ability to do partial writes to addresses that have already been written to.
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@@ -135,7 +135,7 @@ class simulation():
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def add_wmask(self, wmask, port):
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""" Add the array of address values """
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debug.check(len(wmask) == self.num_wmask, "Invalid wmask size.")
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debug.check(len(wmask) == self.num_wmasks, "Invalid wmask size.")
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bit = self.addr_size - 1
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for c in wmask:
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@@ -144,7 +144,8 @@ class simulation():
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elif c == "1":
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self.wmask_values[port][bit].append(1)
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else:
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debug.error("Non-binary address string", 1)
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print(c)
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#debug.error("Non-binary wmask string", 1)
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bit -= 1
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def add_write(self, comment, address, data, port):
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@@ -208,10 +209,24 @@ class simulation():
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debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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def add_partial_write_one_port(self, comment, address, data, wmask, port):
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""" Add the control values for a write cycle (partial). Does not increment the period. """
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debug.check(port in self.write_ports,
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"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
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self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data, port)
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self.add_address(address, port)
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#self.add_wmask(wmask,port)
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def add_read_one_port(self, comment, address, din_data, port):
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""" Add the control values for a read cycle. Does not increment the period. """
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@@ -249,22 +264,20 @@ class simulation():
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t_current,
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t_current+self.period)
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elif op == "write":
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if self.write_size is not None:
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comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
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addr,
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wmask,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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else:
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "partial_write":
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comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
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addr,
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wmask,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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else:
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comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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