mirror of https://github.com/VLSIDA/OpenRAM.git
329 lines
15 KiB
Python
329 lines
15 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys,re,shutil
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from design import design
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import debug
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import math
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import tech
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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class simulation():
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def __init__(self, sram, spfile, corner):
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self.sram = sram
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self.name = self.sram.name
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self.word_size = self.sram.word_size
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self.addr_size = self.sram.addr_size
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self.write_size = self.sram.write_size
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self.num_cols = self.sram.num_cols
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self.num_rows = self.sram.num_rows
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self.num_banks = self.sram.num_banks
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self.sp_file = spfile
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self.all_ports = self.sram.all_ports
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self.readwrite_ports = self.sram.readwrite_ports
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self.read_ports = self.sram.read_ports
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self.write_ports = self.sram.write_ports
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if self.write_size is not None:
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self.num_wmasks = int(self.word_size/self.write_size)
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else:
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self.num_wmasks = 0
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def set_corner(self,corner):
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""" Set the corner values """
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self.corner = corner
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(self.process, self.vdd_voltage, self.temperature) = corner
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def set_spice_constants(self):
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""" sets feasible timing parameters """
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self.period = tech.spice["feasible_period"]
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self.slew = tech.spice["rise_time"]*2
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self.load = tech.spice["msflop_in_cap"]*4
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self.v_high = self.vdd_voltage - tech.spice["v_threshold_typical"]
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self.v_low = tech.spice["v_threshold_typical"]
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self.gnd_voltage = 0
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def create_signal_names(self):
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self.addr_name = "A"
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self.din_name = "DIN"
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self.dout_name = "DOUT"
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self.pins = self.gen_pin_names(port_signal_names=(self.addr_name,self.din_name,self.dout_name),
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port_info=(len(self.all_ports),self.write_ports,self.read_ports),
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abits=self.addr_size,
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dbits=self.word_size)
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debug.check(len(self.sram.pins) == len(self.pins), "Number of pins generated for characterization \
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do match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins,self.pins))
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#This is TODO once multiport control has been finalized.
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#self.control_name = "CSB"
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def set_stimulus_variables(self):
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# Clock signals
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self.cycle_times = []
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self.t_current = 0
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# control signals: only one cs_b for entire multiported sram, one we_b for each write port
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self.csb_values = [[] for port in self.all_ports]
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self.web_values = [[] for port in self.readwrite_ports]
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# Three dimensional list to handle each addr and data bits for wach port over the number of checks
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self.addr_values = [[[] for bit in range(self.addr_size)] for port in self.all_ports]
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self.data_values = [[[] for bit in range(self.word_size)] for port in self.write_ports]
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self.wmask_values = [[[] for bit in range(self.num_wmasks)] for port in self.write_ports]
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# For generating comments in SPICE stimulus
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self.cycle_comments = []
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self.fn_cycle_comments = []
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def add_control_one_port(self, port, op):
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"""Appends control signals for operation to a given port"""
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#Determine values to write to port
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web_val = 1
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csb_val = 1
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if op == "read":
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csb_val = 0
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elif op == "write":
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csb_val = 0
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web_val = 0
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elif op != "noop":
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debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1)
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# Append the values depending on the type of port
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self.csb_values[port].append(csb_val)
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# If port is in both lists, add rw control signal. Condition indicates its a RW port.
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if port in self.readwrite_ports:
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self.web_values[port].append(web_val)
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def add_data(self, data, port):
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""" Add the array of data values """
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debug.check(len(data)==self.word_size, "Invalid data word size.")
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bit = self.word_size - 1
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for c in data:
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if c=="0":
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self.data_values[port][bit].append(0)
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elif c=="1":
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self.data_values[port][bit].append(1)
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else:
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debug.error("Non-binary data string",1)
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bit -= 1
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def add_address(self, address, port):
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""" Add the array of address values """
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debug.check(len(address)==self.addr_size, "Invalid address size.")
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bit = self.addr_size - 1
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for c in address:
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if c=="0":
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self.addr_values[port][bit].append(0)
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elif c=="1":
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self.addr_values[port][bit].append(1)
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else:
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debug.error("Non-binary address string",1)
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bit -= 1
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def add_wmask(self, wmask, port):
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""" Add the array of address values """
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debug.check(len(wmask) == self.num_wmasks, "Invalid wmask size.")
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bit = self.addr_size - 1
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for c in wmask:
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if c == "0":
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self.wmask_values[port][bit].append(0)
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elif c == "1":
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self.wmask_values[port][bit].append(1)
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else:
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print(c)
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#debug.error("Non-binary wmask string", 1)
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bit -= 1
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def add_write(self, comment, address, data, port):
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""" Add the control values for a write cycle. """
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debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.append_cycle_comment(port, comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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for unselected_port in self.all_ports:
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if unselected_port != port:
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self.add_noop_one_port(address, noop_data, unselected_port)
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def add_read(self, comment, address, din_data, port):
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""" Add the control values for a read cycle. """
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debug.check(port in self.read_ports, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.append_cycle_comment(port, comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "read")
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#If the port is also a readwrite then add data.
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if port in self.write_ports:
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self.add_data(din_data,port)
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self.add_address(address, port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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for unselected_port in self.all_ports:
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if unselected_port != port:
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self.add_noop_one_port(address, noop_data, unselected_port)
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def add_noop_all_ports(self, comment, address, data):
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""" Add the control values for a noop to all ports. """
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.append_cycle_comment("All", comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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for port in self.all_ports:
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self.add_noop_one_port(address, data, port)
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def add_write_one_port(self, comment, address, data, port):
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""" Add the control values for a write cycle. Does not increment the period. """
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debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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def add_partial_write_one_port(self, comment, address, data, wmask, port):
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""" Add the control values for a write cycle (partial). Does not increment the period. """
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debug.check(port in self.write_ports,
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"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
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self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data, port)
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self.add_address(address, port)
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#self.add_wmask(wmask,port)
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def add_read_one_port(self, comment, address, din_data, port):
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""" Add the control values for a read cycle. Does not increment the period. """
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debug.check(port in self.read_ports, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "read")
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#If the port is also a readwrite then add data.
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if port in self.write_ports:
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self.add_data(din_data,port)
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self.add_address(address, port)
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def add_noop_one_port(self, address, data, port):
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""" Add the control values for a noop to a single port. Does not increment the period. """
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self.add_control_one_port(port, "noop")
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if port in self.write_ports:
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self.add_data(data,port)
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self.add_address(address, port)
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def append_cycle_comment(self, port, comment):
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"""Add comment to list to be printed in stimulus file"""
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#Clean up time before appending. Make spacing dynamic as well.
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time = "{0:.2f} ns:".format(self.t_current)
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time_spacing = len(time)+6
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self.cycle_comments.append("Cycle {0:<6d} Port {1:<6} {2:<{3}}: {4}".format(len(self.cycle_times),
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port,
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time,
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time_spacing,
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comment))
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def gen_cycle_comment(self, op, word, addr, port, wmask, t_current):
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if op == "noop":
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comment = "\tIdle during cycle {0} ({1}ns - {2}ns)".format(int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "write":
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "partial_write":
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comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
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addr,
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wmask,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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else:
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comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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return comment
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def gen_pin_names(self, port_signal_names, port_info, abits, dbits):
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"""Creates the pins names of the SRAM based on the no. of ports."""
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#This may seem redundant as the pin names are already defined in the sram. However, it is difficult
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#to extract the functionality from the names, so they are recreated. As the order is static, changing
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#the order of the pin names will cause issues here.
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pin_names = []
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(addr_name, din_name, dout_name) = port_signal_names
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(total_ports, write_index, read_index) = port_info
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for write_input in write_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(din_name,write_input, i))
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for port in range(total_ports):
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for i in range(abits):
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pin_names.append("{0}{1}_{2}".format(addr_name,port,i))
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#Control signals not finalized.
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for port in range(total_ports):
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pin_names.append("CSB{0}".format(port))
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for port in range(total_ports):
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if (port in read_index) and (port in write_index):
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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if self.write_size is not None:
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for bit in range(self.num_wmasks):
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pin_names.append("WMASK{0}_{1}".format(port,bit))
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for read_output in read_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(dout_name,read_output, i))
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pin_names.append("{0}".format(tech.spice["vdd_name"]))
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pin_names.append("{0}".format(tech.spice["gnd_name"]))
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return pin_names
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