mirror of https://github.com/VLSIDA/OpenRAM.git
remove remaining cs_buf functions
This commit is contained in:
parent
67c1560df0
commit
71f241f660
|
|
@ -453,12 +453,6 @@ class control_logic_delay(design.design):
|
||||||
mod=self.clk_buf_driver)
|
mod=self.clk_buf_driver)
|
||||||
self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
|
self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
|
||||||
|
|
||||||
def create_cs_buf_row(self): # TODO: place and route
|
|
||||||
""" Create the multistage and gated chip select buffer """
|
|
||||||
self.cs_buf_inst = self.add_inst(name="csbuf",
|
|
||||||
mod=self.clk_buf_driver)
|
|
||||||
self.connect_inst(["cs", "cs_buf", "vdd", "gnd"])
|
|
||||||
|
|
||||||
def place_clk_buf_row(self, row):
|
def place_clk_buf_row(self, row):
|
||||||
x_offset = self.control_x_offset
|
x_offset = self.control_x_offset
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue