From 71f241f660fe4f35dc7377baba1773959effa849 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 21 Jun 2022 21:15:46 -0700 Subject: [PATCH] remove remaining cs_buf functions --- compiler/modules/control_logic_delay.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index c1bac0ed..c47dcafb 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -453,12 +453,6 @@ class control_logic_delay(design.design): mod=self.clk_buf_driver) self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) - def create_cs_buf_row(self): # TODO: place and route - """ Create the multistage and gated chip select buffer """ - self.cs_buf_inst = self.add_inst(name="csbuf", - mod=self.clk_buf_driver) - self.connect_inst(["cs", "cs_buf", "vdd", "gnd"]) - def place_clk_buf_row(self, row): x_offset = self.control_x_offset