Create sized RBL WL driver in port_address

compiler/modules/bank.py

@@ -374,8 +374,6 @@ class bank(design.design):
                                                     port=port))
             self.add_mod(self.port_address[port])
 
-        self.num_rbl = len(self.all_ports)
-
         try:
             local_array_size = OPTS.local_array_size
         except AttributeError:
@@ -875,8 +873,9 @@ class bank(design.design):
     def route_port_address_right(self, port):
         """ Connecting Wordline driver output to Bitcell WL connection  """
 
-        driver_names = ["wl_{}".format(x) for x in range(self.num_rows)]
+        driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + ["rbl_wl"]
-        for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port)):
+        rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port]
+        for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]):
             # The mid guarantees we exit the input cell to the right.
             driver_wl_pin = self.port_address_inst[port].get_pin(driver_name)
             driver_wl_pos = driver_wl_pin.lc()

compiler/modules/global_bitcell_array.py

@@ -267,3 +267,4 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
         for inst in self.local_insts:
             offsets.extend(inst.lx() + x for x in inst.mod.get_column_offsets())
         return offsets
+    

compiler/modules/local_bitcell_array.py

@@ -207,9 +207,9 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
                 
                 y_offset = in_pin.cy()
                 if port == 0:
-                    y_offset -= 1.5 * self.m3_pitch
+                    y_offset -= 2 * self.m3_pitch
                 else:
-                    y_offset += 1.5 * self.m3_pitch
+                    y_offset += 2 * self.m3_pitch
                     
                 self.add_layout_pin_segment_center(text=wl_name,
                                                    layer="m3",

compiler/modules/port_address.py

@@ -79,7 +79,8 @@ class port_address(design.design):
             self.copy_power_pins(inst, "vdd")
             self.copy_power_pins(inst, "gnd")
 
-        self.copy_power_pins(self.rbl_driver_inst, "vdd")
+        rbl_vdd_pin = self.rbl_driver_inst.get_pin("vdd")
+        self.add_power_pin("vdd", rbl_vdd_pin.lc())
 
     def route_pins(self):
         for row in range(self.addr_size):
@@ -111,17 +112,19 @@ class port_address(design.design):
 
         # Route the RBL from the enable input
         en_pin = self.wordline_driver_array_inst.get_pin("en")
+        en_pos = en_pin.center()
         rbl_in_pin = self.rbl_driver_inst.get_pin("A")
         rbl_in_pos = rbl_in_pin.center()
+        
         mid_pos = vector(en_pin.cx(), rbl_in_pin.cy())
-        self.add_path(rbl_in_pin.layer, [rbl_in_pos, mid_pos])
         self.add_via_stack_center(from_layer=rbl_in_pin.layer,
                                   to_layer=en_pin.layer,
-                                  offset=mid_pos)
+                                  offset=rbl_in_pos)
+        self.add_path(en_pin.layer, [rbl_in_pos, mid_pos, en_pos])
         self.add_layout_pin_segment_center(text="wl_en",
                                            layer=en_pin.layer,
                                            start=mid_pos,
-                                           end=en_pin.center())
+                                           end=en_pos)
         
     def add_modules(self):
 

compiler/pgates/wordline_driver.py

@@ -18,7 +18,7 @@ class wordline_driver(design.design):
     This is an AND (or NAND) with configurable drive strength to drive the wordlines.
     It is matched to the bitcell height.
     """
-    def __init__(self, name, cols=1, height=None):
+    def __init__(self, name, cols, height=None):
         debug.info(1, "Creating wordline_driver {}".format(name))
         self.add_comment("cols: {}".format(cols))
         super().__init__(name)

compiler/tests/04_wordline_driver_test.py

@@ -25,7 +25,7 @@ class wordline_driver_test(openram_test):
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
-        tx = factory.create(module_type="wordline_driver")
+        tx = factory.create(module_type="wordline_driver", cols=8)
         self.local_check(tx)
 
         globals.end_openram()

compiler/tests/18_port_address_1rw_1r_test.py

@@ -27,11 +27,11 @@ class port_address_1rw_1r_test(openram_test):
         globals.setup_bitcell()
         
         debug.info(1, "Port address 16 rows")
-        a = factory.create("port_address", cols=16, rows=16)
+        a = factory.create("port_address", cols=16, rows=16, port=0)
         self.local_check(a)
 
         debug.info(1, "Port address 256 rows")
-        a = factory.create("port_address", cols=256, rows=256)
+        a = factory.create("port_address", cols=256, rows=256, port=1)
         self.local_check(a)
         
         globals.end_openram()

compiler/tests/18_port_address_test.py

@@ -21,11 +21,11 @@ class port_address_test(openram_test):
         globals.init_openram(config_file)
 
         debug.info(1, "Port address 16 rows")
-        a = factory.create("port_address", cols=16, rows=16)
+        a = factory.create("port_address", cols=16, rows=16, port=0)
         self.local_check(a)
         
         debug.info(1, "Port address 512 rows")
-        a = factory.create("port_address", cols=256, rows=512)
+        a = factory.create("port_address", cols=256, rows=512, port=0)
         self.local_check(a)
 
         globals.end_openram()