Create sized RBL WL driver in port_address

2026-08-30 01:48:33 +02:00 · 2020-09-28 11:30:21 -07:00
parent c7d32089f3
commit 6f06bb9dd5
8 changed files with 21 additions and 18 deletions
@@ -267,3 +267,4 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
        for inst in self.local_insts:
            offsets.extend(inst.lx() + x for x in inst.mod.get_column_offsets())
        return offsets
+