Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl

compiler/modules/__init__.py

@@ -1,3 +1,8 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 from .and2_dec import *
 from .and3_dec import *
 from .and4_dec import *
@@ -78,5 +83,4 @@ from .write_driver_array import *
 from .write_driver import *
 from .write_mask_and_array import *
 from .sram_1bank import *
-from .sram_config import *
-from .sram import *
+from .internal_base import *

compiler/modules/and2_dec.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and2_dec(design):

compiler/modules/and3_dec.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and3_dec(design):

compiler/modules/and4_dec.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and4_dec(design):

compiler/modules/bank.py

@@ -1,18 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
 from math import log, ceil, floor
-from tech import drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class bank(design):

compiler/modules/bitcell_1port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -29,7 +29,3 @@ class bitcell_1port(bitcell_base):
         """
         self.add_graph_edges(graph, port_nets)
 
-    def is_non_inverting(self):
-        """Return input to output polarity for module"""
-
-        return False

compiler/modules/bitcell_2port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -99,8 +99,3 @@ class bitcell_2port(bitcell_base):
         # Port 1 edges
         graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
         graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
-
-    def is_non_inverting(self):
-        """Return input to output polarity for module"""
-
-        return False

compiler/modules/bitcell_array.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, spice
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):

compiler/modules/bitcell_base.py

@@ -1,16 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-from base import design
-from globals import OPTS
-from base import logical_effort
-from tech import parameter, drc, layer, spice
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, layer, spice
+from openram import OPTS
 
 
 class bitcell_base(design):
@@ -46,7 +45,7 @@ class bitcell_base(design):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         # FIXME
         dynamic = 0
@@ -265,3 +264,15 @@ class bitcell_base(design):
             delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m)
 
         return delay
+
+    def build_graph(self, graph, inst_name, port_nets):
+        """
+        Adds edges based on inputs/outputs.
+        Overrides base class function.
+        """
+        debug.error("Must override build_graph function in bitcell base class.")
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+
+        return False

compiler/modules/bitcell_base_array.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class bitcell_base_array(design):

compiler/modules/col_cap_array.py

@@ -1,11 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class col_cap_array(bitcell_base_array):

compiler/modules/col_cap_bitcell_1port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/col_cap_bitcell_2port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/column_decoder.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2022 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
-from tech import drc
-import debug
-from base import design
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import cell_properties
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import cell_properties
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class column_decoder(design):

compiler/modules/column_mux.py

@@ -1,18 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, layer
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pgate import *
-import debug
-from tech import drc, layer
-from base import vector
-from .pgate import *
-from sram_factory import factory
-from tech import cell_properties as cell_props
-from globals import OPTS
 
 
 class column_mux(pgate):

compiler/modules/column_mux_array.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from tech import layer, preferred_directions
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, preferred_directions
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class column_mux_array(design):

compiler/modules/control_logic.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from sram_factory import factory
 import math
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 from .control_logic_base import control_logic_base
 
 

compiler/modules/control_logic_base.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from sram_factory import factory
 import math
-from base import vector
-from globals import OPTS
-from base import logical_effort
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class control_logic_base(design):

compiler/modules/delay_chain.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class delay_chain(design):

compiler/modules/dff.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import cell_properties as props
-from tech import spice
+from openram.base import design
+from openram.tech import cell_properties as props
+from openram.tech import spice
 
 
 class dff(design):

compiler/modules/dff_array.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_array(design):

compiler/modules/dff_buf.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import layer
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class dff_buf(design):

compiler/modules/dff_buf_array.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_buf_array(design):

compiler/modules/dff_inv.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_inv(design):

compiler/modules/dff_inv_array.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_inv_array(design):

compiler/modules/dummy_array.py

@@ -1,11 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class dummy_array(bitcell_base_array):

compiler/modules/dummy_bitcell_1port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -21,4 +21,6 @@ class dummy_bitcell_1port(bitcell_base):
         super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create dummy bitcell")
 
-
+    def build_graph(self, graph, inst_name, port_nets):
+        """ Adds edges based on inputs/outputs. Overrides base class function. """
+        pass

compiler/modules/dummy_bitcell_2port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -21,4 +21,6 @@ class dummy_bitcell_2port(bitcell_base):
         super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create dummy bitcell 2 port object")
 
-
+    def build_graph(self, graph, inst_name, port_nets):
+        """ Adds edges based on inputs/outputs. Overrides base class function. """
+        pass

compiler/modules/dummy_pbitcell.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dummy_pbitcell(design):

compiler/modules/global_bitcell_array.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .bitcell_base_array import bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
-from base import vector
-import debug
 from numpy import cumsum
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
+from .bitcell_base_array import bitcell_base_array
 
 
 class global_bitcell_array(bitcell_base_array):

compiler/modules/hierarchical_decoder.py

@@ -1,20 +1,21 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import layer_indices
-from tech import layer_stacks
-from tech import layer_properties as layer_props
-from tech import drc
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_indices
+from openram.tech import layer_stacks
+from openram.tech import layer_properties as layer_props
+from openram.tech import drc
+from openram import OPTS
+
 
 class hierarchical_decoder(design):
     """

compiler/modules/hierarchical_predecode.py

@@ -1,21 +1,21 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
 import math
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
-from tech import layer_indices
-from tech import layer_stacks
-from tech import preferred_directions
-from tech import drc
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram.tech import layer_indices
+from openram.tech import layer_stacks
+from openram.tech import preferred_directions
+from openram.tech import drc
+from openram import OPTS
 
 
 class hierarchical_predecode(design):

compiler/modules/hierarchical_predecode2x4.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode2x4(hierarchical_predecode):

compiler/modules/hierarchical_predecode3x8.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode3x8(hierarchical_predecode):

compiler/modules/hierarchical_predecode4x16.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode4x16(hierarchical_predecode):

compiler/modules/internal_base.py

@@ -0,0 +1,14 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from openram.base import design
+
+
+class internal_base(design):
+
+    def __init__(self, name, cell_name=None, prop=None):
+        design.__init__(self, name, cell_name, prop)

compiler/modules/inv_dec.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import logical_effort
-from tech import cell_properties as props
-from tech import spice, parameter
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import spice, parameter
 
 
 class inv_dec(design):

compiler/modules/local_bitcell_array.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
-from base import vector
-import debug
-from tech import layer_properties as layer_props
 
 
 class local_bitcell_array(bitcell_base_array):

compiler/modules/multibank.py

@@ -1,19 +1,20 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import sys
-from tech import drc, parameter
-import debug
-from base import design
 import math
-from math import log,sqrt,ceil
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from math import log, sqrt, ceil
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter
+from openram import OPTS
+
 
 class multibank(design):
     """

compiler/modules/nand2_dec.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand2_dec(design):

compiler/modules/nand3_dec.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand3_dec(design):

compiler/modules/nand4_dec.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand4_dec(design):

compiler/modules/orig_bitcell_array.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):

compiler/modules/pand2.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand2(pgate):

compiler/modules/pand3.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand3(pgate):

compiler/modules/pand4.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand4(pgate):

compiler/modules/pbitcell.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import logical_effort
-from base import vector
-from tech import drc, parameter, layer
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.base import logical_effort
+from openram.base import vector
+from openram.tech import drc, parameter, layer
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .ptx import ptx
 from .bitcell_base import bitcell_base
 

compiler/modules/pbuf.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pbuf(pgate):

compiler/modules/pbuf_dec.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pbuf_dec(pgate):

compiler/modules/pdriver.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from base import vector
-from sram_factory import factory
 
 
 class pdriver(pgate):

compiler/modules/pgate.py

@@ -1,21 +1,21 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import vector
-import debug
 import math
 from bisect import bisect_left
-from tech import layer, drc
-from globals import OPTS
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.tech import layer, drc
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 
 if cell_props.ptx.bin_spice_models:
-    from tech import nmos_bins, pmos_bins
+    from openram.tech import nmos_bins, pmos_bins
 
 
 class pgate(design):

compiler/modules/pinv.py

@@ -1,22 +1,22 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from .pgate import *
-from base import vector
-from base import logical_effort
-from base.utils import round_to_grid
-from base.errors import drc_error
 import operator
-from tech import drc, parameter, spice
 from math import ceil
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.base.utils import round_to_grid
+from openram.base.errors import drc_error
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
+from .pgate import *
 
 
 class pinv(pgate):

compiler/modules/pinv_dec.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, layer
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pinv import pinv
-from tech import drc, parameter, layer
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pinv_dec(pinv):

compiler/modules/pinvbuf.py

@@ -1,15 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
 from .pgate import *
-from base import vector
-from sram_factory import factory
-from tech import layer
+
 
 class pinvbuf(pgate):
     """

compiler/modules/pnand2.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand2(pgate):

compiler/modules/pnand3.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand3(pgate):

compiler/modules/pnand4.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand4(pgate):

compiler/modules/pnor2.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnor2(pgate):

compiler/modules/port_address.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from math import log, ceil
-import debug
-from base import design
-from sram_factory import factory
-from base import vector
-from tech import layer, drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class port_address(design):

compiler/modules/port_data.py

@@ -1,18 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
-from tech import drc
-import debug
-from base import design
 import math
-from sram_factory import factory
 from collections import namedtuple
-from base import vector
-from globals import OPTS
-from tech import cell_properties
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import cell_properties
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class port_data(design):

compiler/modules/precharge.py

@@ -1,18 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import parameter, drc
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pgate import *
-from tech import parameter, drc
-from base import vector
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class precharge(design):

compiler/modules/precharge_array.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class precharge_array(design):

compiler/modules/ptristate_inv.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from sram_factory import factory
 
 
 class ptristate_inv(pgate):

compiler/modules/ptx.py

@@ -1,18 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import logical_effort
-from base import vector
-from tech import layer, drc, spice
-from sram_factory import factory
-from globals import OPTS
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, drc, spice
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 
 
 class ptx(design):

compiler/modules/pwrite_driver.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-#Copyright (c) 2021 Regents of the University of California and The Board
-#of Regents for the Oklahoma Agricultural and Mechanical College
-#(acting for and on behalf of Oklahoma State University)
-#All rights reserved.
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
 #
-from base import design
-from tech import parameter
-import debug
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import parameter
+from openram import OPTS
 
 
 class pwrite_driver(design):

compiler/modules/replica_bitcell_1port.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import parameter, drc
 from .bitcell_base import bitcell_base
-from tech import cell_properties as props
-from tech import parameter, drc
-from base import logical_effort
 
 
 class replica_bitcell_1port(bitcell_base):
@@ -39,7 +39,7 @@ class replica_bitcell_1port(bitcell_base):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         dynamic = 0 # FIXME
         total_power = self.return_power(dynamic, leakage)

compiler/modules/replica_bitcell_2port.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import parameter, drc
 from .bitcell_base import bitcell_base
-from tech import cell_properties as props
-from tech import parameter, drc
-from base import logical_effort
 
 
 class replica_bitcell_2port(bitcell_base):

compiler/modules/replica_bitcell_array.py

@@ -1,17 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
-
-import debug
-from base import vector
-from base import contact
+from openram import debug
+from openram.base import vector
+from openram.base import contact
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from tech import cell_properties as props
-from globals import OPTS
-from sram_factory import factory
 
 
 class replica_bitcell_array(bitcell_base_array):

compiler/modules/replica_column.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import layer_properties as layer_props
 
 
 class replica_column(bitcell_base_array):

compiler/modules/replica_pbitcell.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_pbitcell(design):

compiler/modules/row_cap_array.py

@@ -1,11 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class row_cap_array(bitcell_base_array):

compiler/modules/row_cap_bitcell_1port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/row_cap_bitcell_2port.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/sense_amp.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from tech import parameter, drc, spice
-from tech import cell_properties as props
-from base import logical_effort
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, spice
+from openram.tech import cell_properties as props
 
 
 class sense_amp(design):
@@ -43,7 +43,7 @@ class sense_amp(design):
         # FIXME: This input load will be applied to both the s_en timing and bitline timing.
 
         # Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
-        from tech import spice
+        from openram.tech import spice
         # Default is 8x. Per Samira and Hodges-Jackson book:
         # "Column-mux transistors driven by the decoder must be sized for optimal speed"
         bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file.

compiler/modules/sense_amp_array.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import vector
-from sram_factory import factory
-from tech import cell_properties
-import debug
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import cell_properties
+from openram import OPTS
 
 
 class sense_amp_array(design):

compiler/modules/sram.py

@@ -1,180 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-import datetime
-import os
-import debug
-from characterizer import functional
-from globals import OPTS, print_time
-import shutil
-
-
-class sram():
-    """
-    This is not a design module, but contains an SRAM design instance.
-    It could later try options of number of banks and oganization to compare
-    results.
-    We can later add visualizer and other high-level functions as needed.
-    """
-    def __init__(self, sram_config, name):
-
-        sram_config.set_local_config(self)
-
-        # reset the static duplicate name checker for unit tests
-        # in case we create more than one SRAM
-        from base import design
-        design.name_map=[]
-
-        debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
-                                                                                       self.num_words,
-                                                                                       self.num_banks))
-        start_time = datetime.datetime.now()
-
-        self.name = name
-
-        from .sram_1bank import sram_1bank as sram
-
-        self.s = sram(name, sram_config)
-
-        self.s.create_netlist()
-        if not OPTS.netlist_only:
-            self.s.create_layout()
-
-        if not OPTS.is_unit_test:
-            print_time("SRAM creation", datetime.datetime.now(), start_time)
-
-    def sp_write(self, name, lvs=False, trim=False):
-        self.s.sp_write(name, lvs, trim)
-
-    def lef_write(self, name):
-        self.s.lef_write(name)
-
-    def gds_write(self, name):
-        self.s.gds_write(name)
-
-    def verilog_write(self, name):
-        self.s.verilog_write(name)
-        if self.num_banks != 1:
-            from .sram_multibank import sram_multibank
-            mb = sram_multibank(self.s)
-            mb.verilog_write(name[:-2] + '_top.v')
-
-    def extended_config_write(self, name):
-        """Dump config file with all options.
-           Include defaults and anything changed by input config."""
-        f = open(name, "w")
-        var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
-        for var_name, var_value in var_dict.items():
-            if isinstance(var_value, str):
-                f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
-            else:
-                f.write(str(var_name) + " = " + str(var_value)+ "\n")
-        f.close()
-
-    def save(self):
-        """ Save all the output files while reporting time to do it as well. """
-
-        # Import this at the last minute so that the proper tech file
-        # is loaded and the right tools are selected
-        import verify
-
-        # Save the spice file
-        start_time = datetime.datetime.now()
-        spname = OPTS.output_path + self.s.name + ".sp"
-        debug.print_raw("SP: Writing to {0}".format(spname))
-        self.sp_write(spname)
-        functional(self.s,
-                   os.path.basename(spname),
-                   cycles=200,
-                   output_path=OPTS.output_path)
-        print_time("Spice writing", datetime.datetime.now(), start_time)
-
-        if not OPTS.netlist_only:
-            # Write the layout
-            start_time = datetime.datetime.now()
-            gdsname = OPTS.output_path + self.s.name + ".gds"
-            debug.print_raw("GDS: Writing to {0}".format(gdsname))
-            self.gds_write(gdsname)
-            if OPTS.check_lvsdrc:
-                verify.write_drc_script(cell_name=self.s.name,
-                                        gds_name=os.path.basename(gdsname),
-                                        extract=True,
-                                        final_verification=True,
-                                        output_path=OPTS.output_path)
-            print_time("GDS", datetime.datetime.now(), start_time)
-
-            # Create a LEF physical model
-            start_time = datetime.datetime.now()
-            lefname = OPTS.output_path + self.s.name + ".lef"
-            debug.print_raw("LEF: Writing to {0}".format(lefname))
-            self.lef_write(lefname)
-            print_time("LEF", datetime.datetime.now(), start_time)
-
-        # Save the LVS file
-        start_time = datetime.datetime.now()
-        lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
-        debug.print_raw("LVS: Writing to {0}".format(lvsname))
-        self.sp_write(lvsname, lvs=True)
-        if not OPTS.netlist_only and OPTS.check_lvsdrc:
-            verify.write_lvs_script(cell_name=self.s.name,
-                                    gds_name=os.path.basename(gdsname),
-                                    sp_name=os.path.basename(lvsname),
-                                    final_verification=True,
-                                    output_path=OPTS.output_path)
-        print_time("LVS writing", datetime.datetime.now(), start_time)
-
-        # Save the extracted spice file
-        if OPTS.use_pex:
-            start_time = datetime.datetime.now()
-            # Output the extracted design if requested
-            pexname = OPTS.output_path + self.s.name + ".pex.sp"
-            spname = OPTS.output_path + self.s.name + ".sp"
-            verify.run_pex(self.s.name, gdsname, spname, output=pexname)
-            sp_file = pexname
-            print_time("Extraction", datetime.datetime.now(), start_time)
-        else:
-            # Use generated spice file for characterization
-            sp_file = spname
-
-        # Save a functional simulation file
-
-        # Characterize the design
-        start_time = datetime.datetime.now()
-        from characterizer import lib
-        debug.print_raw("LIB: Characterizing... ")
-        lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
-        print_time("Characterization", datetime.datetime.now(), start_time)
-
-        # Write the config file
-        start_time = datetime.datetime.now()
-        from shutil import copyfile
-        copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
-        debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
-        print_time("Config", datetime.datetime.now(), start_time)
-
-        # Write the datasheet
-        start_time = datetime.datetime.now()
-        from datasheet import datasheet_gen
-        dname = OPTS.output_path + self.s.name + ".html"
-        debug.print_raw("Datasheet: Writing to {0}".format(dname))
-        datasheet_gen.datasheet_write(dname)
-        print_time("Datasheet", datetime.datetime.now(), start_time)
-
-        # Write a verilog model
-        start_time = datetime.datetime.now()
-        vname = OPTS.output_path + self.s.name + '.v'
-        debug.print_raw("Verilog: Writing to {0}".format(vname))
-        self.verilog_write(vname)
-        print_time("Verilog", datetime.datetime.now(), start_time)
-
-        # Write out options if specified
-        if OPTS.output_extended_config:
-            start_time = datetime.datetime.now()
-            oname = OPTS.output_path + OPTS.output_name + "_extended.py"
-            debug.print_raw("Extended Config: Writing to {0}".format(oname))
-            self.extended_config_write(oname)
-            print_time("Extended Config", datetime.datetime.now(), start_time)

compiler/modules/sram_1bank.py

@@ -1,23 +1,23 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import vector
-from base import channel_route
-from router import router_tech
-from globals import OPTS, print_time
 import datetime
-import debug
 from math import ceil
-from importlib import reload
-from base import design
-from base import verilog
-from base import lef
-from sram_factory import factory
-from tech import spice
+from importlib import import_module, reload
+from openram import debug
+from openram.base import vector
+from openram.base import channel_route
+from openram.base import design
+from openram.base import verilog
+from openram.base import lef
+from openram.router import router_tech
+from openram.sram_factory import factory
+from openram.tech import spice
+from openram import OPTS, print_time
 
 
 class sram_1bank(design, verilog, lef):
@@ -43,7 +43,7 @@ class sram_1bank(design, verilog, lef):
             self.num_spare_cols = 0
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults
@@ -254,9 +254,9 @@ class sram_1bank(design, verilog, lef):
             # Do not route the power supply (leave as must-connect pins)
             return
         elif OPTS.route_supplies == "grid":
-            from router import supply_grid_router as router
+            from openram.router import supply_grid_router as router
         else:
-            from router import supply_tree_router as router
+            from openram.router import supply_tree_router as router
         rtr=router(layers=self.supply_stack,
                    design=self,
                    bbox=bbox,
@@ -367,7 +367,7 @@ class sram_1bank(design, verilog, lef):
                     for bit in range(self.num_spare_cols):
                         pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
 
-        from router import signal_escape_router as router
+        from openram.router import signal_escape_router as router
         rtr=router(layers=self.m3_stack,
                    design=self,
                    bbox=bbox)
@@ -482,7 +482,7 @@ class sram_1bank(design, verilog, lef):
 
         self.bank_count = 0
 
-        c = reload(__import__('modules.' + OPTS.control_logic))
+        c = reload(import_module("." + OPTS.control_logic, "openram.modules"))
         self.mod_control_logic = getattr(c, OPTS.control_logic)
 
         # Create the control logic module for each port type

compiler/modules/sram_config.py

@@ -1,177 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-import debug
-from math import log, sqrt, ceil
-from globals import OPTS
-from sram_factory import factory
-
-
-class sram_config:
-    """ This is a structure that is used to hold the SRAM configuration options. """
-
-    def __init__(self, word_size, num_words, write_size=None, num_banks=1, words_per_row=None, num_spare_rows=0, num_spare_cols=0):
-        self.word_size = word_size
-        self.num_words = num_words
-        # Don't add a write mask if it is the same size as the data word
-        self.write_size_init = write_size
-        if write_size:
-            self.write_size = write_size
-        else:
-            self.write_size = word_size
-        self.num_banks = num_banks
-        self.num_spare_rows = num_spare_rows
-        self.num_spare_cols = num_spare_cols
-
-        try:
-            from tech import array_row_multiple
-            self.array_row_multiple = array_row_multiple
-        except ImportError:
-            self.array_row_multiple = 1
-        try:
-            from tech import array_col_multiple
-            self.array_col_multiple = array_col_multiple
-        except ImportError:
-            self.array_col_multiple = 1
-
-
-        # This will get over-written when we determine the organization
-        self.words_per_row = words_per_row
-
-        self.compute_sizes()
-
-    def __str__(self):
-        """ override print function output """
-        config_items = ["num_banks",
-                        "word_size",
-                        "num_words",
-                        "words_per_row",
-                        "write_size",
-                        "num_spare_rows",
-                        "num_spare_cols"]
-        str = ""
-        for item in config_items:
-            val = getattr(self, item)
-            str += "{} : {}\n".format(item, val)
-        return str
-
-    def set_local_config(self, module):
-        """ Copy all of the member variables to the given module for convenience """
-
-        members = [attr for attr in dir(self) if not callable(getattr(self, attr)) and not attr.startswith("__")]
-
-        # Copy all the variables to the local module
-        for member in members:
-            setattr(module, member, getattr(self, member))
-
-    def compute_sizes(self):
-        """  Computes the organization of the memory using bitcell size by trying to make it square."""
-
-        bitcell = factory.create(module_type=OPTS.bitcell)
-
-        debug.check(ceil(log(self.num_banks, 2)) == log(self.num_banks, 2) ,
-                    "Number of banks should be power of 2.")
-
-        self.num_words_per_bank = self.num_words / self.num_banks
-        self.num_bits_per_bank = self.word_size * self.num_words_per_bank
-
-        # If this was hard coded, don't dynamically compute it!
-        if not self.words_per_row:
-            # Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry)
-            self.bank_area = bitcell.width * bitcell.height * self.num_bits_per_bank
-            self.bank_side_length = sqrt(self.bank_area)
-
-            # Estimate the words per row given the height of the bitcell and the square side length
-            self.tentative_num_cols = int(self.bank_side_length / bitcell.width)
-            self.words_per_row = self.estimate_words_per_row(self.tentative_num_cols, self.word_size)
-
-            # Estimate the number of rows given the tentative words per row
-            self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row * self.word_size)
-            self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
-
-        self.recompute_sizes()
-
-        # Set word_per_row in OPTS
-        OPTS.words_per_row = self.words_per_row
-        debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row))
-
-    def recompute_sizes(self):
-        """
-        Calculate the auxiliary values assuming fixed number of words per row.
-        This can be called multiple times from the unit test when we reconfigure an
-        SRAM for testing.
-        """
-
-        debug.info(1, "Recomputing with words per row: {}".format(self.words_per_row))
-
-        # If the banks changed
-        self.num_words_per_bank = self.num_words / self.num_banks
-        self.num_bits_per_bank = self.word_size * self.num_words_per_bank
-
-        # Fix the number of columns and rows
-        self.num_cols = int(self.words_per_row * self.word_size)
-        self.num_rows_temp = int(self.num_words_per_bank / self.words_per_row)
-        self.num_rows = self.num_rows_temp + self.num_spare_rows
-        debug.info(1, "Rows: {} Cols: {}".format(self.num_rows_temp, self.num_cols))
-
-        # Fix the write_size
-        if self.write_size_init:
-            self.write_size = self.write_size_init
-        else:
-            self.write_size = self.word_size
-
-        # Compute the address and bank sizes
-        self.row_addr_size = ceil(log(self.num_rows, 2))
-        self.col_addr_size = int(log(self.words_per_row, 2))
-        self.bank_addr_size = self.col_addr_size + self.row_addr_size
-        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
-        #self.addr_size = self.bank_addr_size
-        debug.info(1, "Row addr size: {}".format(self.row_addr_size)
-                   + " Col addr size: {}".format(self.col_addr_size)
-                   + " Bank addr size: {}".format(self.bank_addr_size))
-
-        num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
-        if num_ports == 1:
-            if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0):
-                debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, self.array_col_multiple), -1)
-
-            if ((self.num_rows + num_ports) % self.array_row_multiple != 0):
-                debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, self.array_row_multiple), -1)
-
-    def estimate_words_per_row(self, tentative_num_cols, word_size):
-        """
-        This provides a heuristic rounded estimate for the number of words
-        per row.
-        """
-        tentative_column_ways = tentative_num_cols / word_size
-        column_mux_sizes = [1, 2, 4, 8, 16]
-        # If we are double, we may want a larger column mux
-        if tentative_column_ways > 2 * column_mux_sizes[-1]:
-            debug.warning("Extremely large number of columns for 16-way maximum column mux.")
-
-        closest_way = min(column_mux_sizes, key=lambda x: abs(x - tentative_column_ways))
-
-        return closest_way
-
-    def amend_words_per_row(self, tentative_num_rows, words_per_row):
-        """
-        This picks the number of words per row more accurately by limiting
-        it to a minimum and maximum.
-        """
-        # Recompute the words per row given a hard max
-        if(not OPTS.is_unit_test and tentative_num_rows > 512):
-            debug.check(tentative_num_rows * words_per_row <= 4096,
-                        "Number of words exceeds 2048")
-            return int(words_per_row * tentative_num_rows / 512)
-
-        # Recompute the words per row given a hard min
-        if (not OPTS.is_unit_test and tentative_num_rows < 16):
-            debug.check(tentative_num_rows * words_per_row >= 16,
-                        "Minimum number of rows is 16, but given {0}".format(tentative_num_rows))
-            return int(words_per_row * tentative_num_rows / 16)
-
-        return words_per_row

compiler/modules/sram_multibank.py

@@ -1,8 +1,13 @@
-from .template import template
-from globals import OPTS
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 import os
-from math import ceil, log
 import re
+from math import ceil, log
+from openram import OPTS
+from .template import template
 
 
 class sram_multibank:

compiler/modules/template.py

@@ -1,7 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California
-# Santa Cruz
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 import re

compiler/modules/tri_gate.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import spice
+from openram import debug
+from openram.base import design
+from openram.tech import spice
 
 
 class tri_gate(design):

compiler/modules/tri_gate_array.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import drc
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram import OPTS
 
 class tri_gate_array(design):
     """

compiler/modules/wordline_buffer_array.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import layer
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_buffer_array(design):

compiler/modules/wordline_driver.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_driver(design):

compiler/modules/wordline_driver_array.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import drc, layer
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_driver_array(design):

compiler/modules/write_driver.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import cell_properties as props
+from openram import debug
+from openram.base import design
+from openram.tech import cell_properties as props
 
 
 class write_driver(design):

compiler/modules/write_driver_array.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
 import math
-from tech import drc
-from sram_factory import factory
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram import OPTS
 
 
 class write_driver_array(design):

compiler/modules/write_mask_and_array.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_mask_and_array(design):