diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md new file mode 100644 index 00000000..b080fd3e --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -0,0 +1,27 @@ +--- +name: Bug report +about: Create a report to help us improve +title: '' +labels: '' +assignees: '' + +--- + +**Describe the bug** +A clear and concise description of what the bug is. + +**Version** +Which commit are you using? + +**To Reproduce** +What did you do to demonstrate the bug? +Please include your configuration file used. + +**Expected behavior** +A clear and concise description of what you expected to happen. + +**Logs** +If applicable, add logs or output to help explain your problem. + +**Additional context** +Add any other context about the problem here. diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 0d4852d8..1ee401d1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -6,6 +6,9 @@ jobs: steps: - name: Checkout code uses: actions/checkout@v1 + - name: Library build + run: | + make library - name: Docker build run: | cd ${{ github.workspace }}/docker diff --git a/.gitignore b/.gitignore index 7a6ad08b..b2ddb51b 100644 --- a/.gitignore +++ b/.gitignore @@ -14,5 +14,10 @@ technology/sky130/*_lib technology/sky130/tech/.magicrc .idea compiler/tests/results/ -sky*/ open_pdks/ +dist/ +openram.egg-info/ +sky130A/ +sky130B/ +skywater-pdk/ +sky130_fd_bd_sram/ diff --git a/HINTS.md b/HINTS.md deleted file mode 100644 index 6f29c16b..00000000 --- a/HINTS.md +++ /dev/null @@ -1,117 +0,0 @@ -# Debugging - -When OpenRAM runs, it puts files in a temporary directory that is -shown in the banner at the top. Like: -``` - /tmp/openram_mrg_18128_temp/ -``` -This is where simulations and DRC/LVS get run so there is no network -traffic. The directory name is unique for each person and run of -OpenRAM to not clobber any files and allow simultaneous runs. If it -passes, the files are deleted. If it fails, you will see these files: -+ temp.gds is the layout (.mag files too if using SCMOS) -+ temp.sp is the netlist -+ test1.drc.err is the std err output of the DRC command -+ test1.drc.out is the standard output of the DRC command -+ test1.drc.results is the DRC results file -+ test1.lvs.err is the std err output of the LVS command -+ test1.lvs.out is the standard output of the LVS command -+ test1.lvs.results is the DRC results file - -Depending on your DRC/LVS tools, there will also be: -+ \_calibreDRC.rul\_ is the DRC rule file (Calibre) -+ dc_runset is the command file (Calibre) -+ extracted.sp (Calibre) -+ run_lvs.sh is a Netgen script for LVS (Netgen) -+ run_drc.sh is a Magic script for DRC (Magic) -+ .spice (Magic) - -If DRC/LVS fails, the first thing is to check if it ran in the .out and -.err file. This shows the standard output and error output from -running DRC/LVS. If there is a setup problem it will be shown here. - -If DRC/LVS runs, but doesn't pass, you then should look at the .results -file. If the DRC fails, it will typically show you the command that was used -to run Calibre or Magic+Netgen. - -To debug, you will need a layout viewer. I prefer to use Glade -on my Mac, but you can also use Calibre, Magic, etc. - -1. Klayout - - You can view the designs in [Klayout](https://www.klayout.de/) with the configuration - file provided in the tech directories. For example, -``` - klayout temp.gds -l /home/vagrant/openram/technology/freepdk45/tf/FreePDK45.lyp -``` - -2. Calibre - - Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file: -``` - calibredrv temp.gds -``` - Select Verification->Start RVE and select the results database file in - the new form (e.g., test1.drc.db). This will start the RVE (results - viewer). Scroll through the check pane and find the DRC check with an - error. Select it and it will open some numbers to the right. Double - click on any of the errors in the result browser. These will be - labelled as numbers "1 2 3 4" for example will be 4 DRC errors. - - In the viewer ">" opens the layout down a level. - -3. Glade - - You can view errors in [Glade](http://www.peardrop.co.uk/glade/) as well. - - To remote display over X windows, you need to disable OpenGL acceleration or use vnc - or something. You can disable by adding this to your .bashrc in bash: -``` - export GLADE_USE_OPENGL=no -``` - or in .cshrc/.tcshrc in csh/tcsh: -``` - setenv GLADE_USE_OPENGAL no -``` - To use this with the FreePDK45 or SCMOS layer views you should use the - tech files. Then create a .glade.py file in your user directory with - these commands to load the technology layers: -``` -ui().importCds("default", -"/Users/mrg/techfiles/freepdk45/display.drf", -"/Users/mrg/techfiles/freepdk45/FreePDK45.tf", 1000, 1, -"/Users/mrg/techfiles/freepdk45/layers.map") -``` - Obviously, edit the paths to point to your directory. To switch - between processes, you have to change the importCds command (or you - can manually run the command each time you start glade). - - To load the errors, you simply do Verify->Import Calibre Errors select - the .results file from Calibre. - -4. Magic - - Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules - and [Magic](http://opencircuitdesign.com/) - - When running DRC or extraction, OpenRAM will load the GDS file, save - the .ext/.mag files, and export an extracted netlist (.spice). - -5. It is possible to use other viewers as well, such as: - * [LayoutEditor](http://www.layouteditor.net/) - - -# Example to output/input .gds layout files from/to Cadence - -1. To create your component layouts, you should stream them to - individual gds files using our provided layermap and flatten - cells. For example, -``` - strmout -layerMap layers.map -library sram -topCell $i -view layout -flattenVias -flattenPcells -strmFile ../gds_lib/$i.gds -``` -2. To stream a layout back into Cadence, do this: -``` - strmin -layerMap layers.map -attachTechFileOfLib NCSU\_TechLib\_FreePDK45 -library sram_4_32 -strmFile sram_4_32.gds -``` - When you import a gds file, make sure to attach the correct tech lib - or you will get incorrect layers in the resulting library. diff --git a/MANIFEST.in b/MANIFEST.in new file mode 100644 index 00000000..b2d45363 --- /dev/null +++ b/MANIFEST.in @@ -0,0 +1,24 @@ +include Makefile +include openram.mk +include setpaths.sh +include requirements.txt +include docker/* +recursive-include compiler * +recursive-include technology * +exclude .DS_Store +exclude .idea +exclude **/model_data +exclude technology/sky130/*_lib +exclude technology/sky130/tech/.magicrc +exclude compiler/gen_stimulus.py +exclude compiler/model_data_util.py +exclude compiler/printGDS.py +exclude compiler/processGDS.py +exclude compiler/uniquifyGDS.py +exclude compiler/view_profile.py +exclude compiler/run_profile.sh +recursive-exclude open_pdks * +recursive-exclude compiler/tests/results * +recursive-exclude technology/freepdk45/ncsu_basekit * +recursive-exclude outputs * +global-exclude *.pyc *~ *.orig *.rej *.aux *.out *.toc *.synctex.gz \ No newline at end of file diff --git a/Makefile b/Makefile index 214b834b..cdd527c1 100644 --- a/Makefile +++ b/Makefile @@ -58,16 +58,14 @@ $(SKY130_PDKS_DIR): check-pdk-root @echo "Cloning skywater PDK..." @[ -d $(PDK_ROOT)/skywater-pdk ] || \ git clone https://github.com/google/skywater-pdk.git $(PDK_ROOT)/skywater-pdk - @cd $(SKY130_PDKS_DIR) && \ - git checkout main && git pull && \ - git checkout -qf $(SKY130_PDKS_GIT_COMMIT) && \ - git submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest + @git -C $(SKY130_PDKS_DIR) checkout $(SKY130_PDKS_GIT_COMMIT) && \ + git -C $(SKY130_PDKS_DIR) submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest $(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR) @echo "Cloning open_pdks..." @[ -d $(OPEN_PDKS_DIR) ] || \ git clone $(OPEN_PDKS_GIT_REPO) $(OPEN_PDKS_DIR) - @cd $(OPEN_PDKS_DIR) && git pull && git checkout $(OPEN_PDKS_GIT_COMMIT) + @git -C $(OPEN_PDKS_DIR) checkout $(OPEN_PDKS_GIT_COMMIT) $(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR) @echo "Installing open_pdks..." @@ -80,11 +78,11 @@ $(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR) $(SRAM_LIB_DIR): check-pdk-root @echo "Cloning SRAM library..." - @[ -d $(SRAM_LIB_DIR) ] || (\ - git clone $(SRAM_LIB_GIT_REPO) $(SRAM_LIB_DIR) && \ - cd $(SRAM_LIB_DIR) && git pull && git checkout $(SRAM_LIB_GIT_COMMIT)) + @[ -d $(SRAM_LIB_DIR) ] || \ + git clone $(SRAM_LIB_GIT_REPO) $(SRAM_LIB_DIR) + @git -C $(SRAM_LIB_DIR) checkout $(SRAM_LIB_GIT_COMMIT) -install: $(SRAM_LIB_DIR) pdk +install: $(SRAM_LIB_DIR) @[ -d $(PDK_ROOT)/sky130A ] || \ (echo "Warning: $(PDK_ROOT)/sky130A not found!! Run make pdk first." && false) @[ -d $(PDK_ROOT)/skywater-pdk ] || \ @@ -215,3 +213,16 @@ wipe: uninstall @rm -rf $(OPEN_PDKS_DIR) @rm -rf $(SKY130_PDKS_DIR) .PHONY: wipe + +# Build the openram library +build-library: + @rm -rf dist + @rm -rf openram.egg-info + @python3 -m pip install --upgrade build + @python3 -m build +.PHONY: build-library + +# Build and install the openram library +library: build-library + @python3 -m pip install --force --find-links=dist openram +.PHONY: library diff --git a/README.md b/README.md index e77ad7c6..895b9f1d 100644 --- a/README.md +++ b/README.md @@ -19,169 +19,8 @@ predictive and fabricable technologies. # Documentation -Please take a look at our presentation We have created a detailed -presentation that serves as our [documentation][documentation]. -This is the most up-to-date information, so please let us know if you see -things that need to be fixed. - -# Basic Setup - -## Dependencies - -Please see the Dockerfile for the required versions of tools. - -In general, the OpenRAM compiler has very few dependencies: -+ Docker -+ Make -+ Python 3.6 or higher -+ Various Python packages (pip install -r requirements.txt) -+ [Git] - -## Docker - -We have a [docker setup](./docker) to run OpenRAM. To use this, you should run: -``` -cd OpenRAM/docker -make build -``` -This must be run once and will take a while to build all the tools. - - -## Environment - -You must set two environment variables: -+ OPENRAM\_HOME should point to the compiler source directory. -+ OPENERAM\_TECH should point to one or more root technology directories (colon separated). - -You should also add OPENRAM\_HOME to your PYTHONPATH. - -For example add this to your .bashrc: - -``` - export OPENRAM_HOME="$HOME/OpenRAM/compiler" - export OPENRAM_TECH="$HOME/OpenRAM/technology" -``` - -You should also add OPENRAM\_HOME to your PYTHONPATH: -``` - export PYTHONPATH=$OPENRAM_HOME -``` - -Note that if you want symbols to resolve in your editor, you may also want to add the specific technology -directory that you use and any custom technology modules as well. For example: -``` - export PYTHONPATH="$OPENRAM_HOME:$OPENRAM_TECH/sky130:$OPENRAM_TECH/sky130/custom" -``` - -We include the tech files necessary for [SCMOS] SCN4M_SUBM, -[FreePDK45]. The [SCMOS] spice models, however, are -generic and should be replaced with foundry models. You may get the -entire [FreePDK45 PDK here][FreePDK45]. - - -### Sky130 Setup - -To install [Sky130], you must have the open_pdks files installed in $PDK_ROOT. -To install this automatically, you can run: - -``` -cd $HOME/OpenRAM -make pdk -``` - -Then you must also install the [Sky130] SRAM build space and the appropriate cell views -by running: - -``` -cd $HOME/OpenRAM -make install -``` - -# Basic Usage - -Once you have defined the environment, you can run OpenRAM from the command line -using a single configuration file written in Python. - -For example, create a file called *myconfig.py* specifying the following -parameters for your memory: -``` -# Data word size -word_size = 2 -# Number of words in the memory -num_words = 16 - -# Technology to use in $OPENRAM_TECH -tech_name = "scn4m_subm" - -# You can use the technology nominal corner only -nominal_corner_only = True -# Or you can specify particular corners -# Process corners to characterize -# process_corners = ["SS", "TT", "FF"] -# Voltage corners to characterize -# supply_voltages = [ 3.0, 3.3, 3.5 ] -# Temperature corners to characterize -# temperatures = [ 0, 25 100] - -# Output directory for the results -output_path = "temp" -# Output file base name -output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) - -# Disable analytical models for full characterization (WARNING: slow!) -# analytical_delay = False - -``` - -You can then run OpenRAM by executing: -``` -python3 $OPENRAM_HOME/openram.py myconfig -``` -You can see all of the options for the configuration file in -$OPENRAM\_HOME/options.py - -To run designs in Docker, it is suggested to use, for example: -``` -cd OpenRAM/macros -make example_config_scn4m_subm -``` - -# Unit Tests - -Regression testing performs a number of tests for all modules in OpenRAM. -From the unit test directory ($OPENRAM\_HOME/tests), -use the following command to run all regression tests: - -``` -cd OpenRAM/compiler/tests -make -j 3 -``` -The -j can run with 3 threads. By default, this will run in all technologies. - -To run a specific test in all technologies: -``` -cd OpenRAM/compiler/tests -make 05_bitcell_array_test -``` -To run a specific technology: -``` -cd OpenRAM/compiler/tests -TECHS=scn4m_subm make 05_bitcell_array_test -``` - -To increase the verbosity of the test, add one (or more) -v options and -pass it as an argument to OpenRAM: -``` -ARGS="-v" make 05_bitcell_array_test -``` - -Unit test results are put in a directory: -``` -OpenRAM/compiler/tests/results// -``` -If the test fails, there will be a tmp directory with intermediate results. -If the test passes, this directory will be deleted to save space. -You can view the .out file to see what the output of a test is in either case. +Please see our [documentation][documentation] and let us know if anything needs +updating. # Get Involved @@ -194,17 +33,25 @@ You can view the .out file to see what the output of a test is in either case. # Further Help -+ [Additional hints](./HINTS.md) + [Documentation][documentation] + [OpenRAM Slack Workspace][Slack] + [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe]) + [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe]) -+ @mrg@fostodon.org # License OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). +# Publications + ++ M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016 ++ S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506. ++ E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017 ++ B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization", IEEE International Symposium on Circuits and Systems (ISCAS), 2019 ++ B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019 ++ H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019 + + # Contributors & Acknowledgment - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect. @@ -223,9 +70,9 @@ If I forgot to add you, please let me know! [Github issues]: https://github.com/VLSIDA/OpenRAM/issues [Github pull request]: https://github.com/VLSIDA/OpenRAM/pulls -[Github project]: https://github.com/VLSIDA/OpenRAM +[Github project]: https://github.com/VLSIDA/OpenRAM -[documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing +[documentation]: docs/source/index.md [dev-group]: mailto:openram-dev-group@ucsc.edu [user-group]: mailto:openram-user-group@ucsc.edu [dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu diff --git a/__init__.py b/__init__.py new file mode 100644 index 00000000..cabfc7fa --- /dev/null +++ b/__init__.py @@ -0,0 +1,31 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import os + +# Attempt to add the source code to the PYTHONPATH here before running globals.init_openram(). +try: + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) +except: + OPENRAM_HOME = os.path.dirname(os.path.abspath(__file__)) + "/compiler" + +if not os.path.isdir(OPENRAM_HOME): + assert False + +# Make sure that OPENRAM_HOME is an environment variable just in case +if "OPENRAM_HOME" not in os.environ.keys(): + os.environ["OPENRAM_HOME"] = OPENRAM_HOME + +# Prepend $OPENRAM_HOME to __path__ so that openram will use those modules +__path__.insert(0, OPENRAM_HOME) + +# Import everything in globals.py +from .globals import * +# Import classes in the "openram" namespace +# sram_config should be imported before sram +from .sram_config import * +from .sram import * diff --git a/compiler/Makefile b/compiler/Makefile index 117e4bd2..d3596421 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -95,7 +95,7 @@ model: $(STAMPS) $(eval bname=$(basename $(notdir $@))) $(eval config_path=$(CONFIG_DIR)/$(addsuffix .py, $(notdir $(basename $@)))) mkdir -p $(SIM_DIR)/$(bname) - -python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $(config_path) 2>&1 > /dev/null + -python3 $(OPENRAM_HOME)/../sram_compiler.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $(config_path) 2>&1 > /dev/null touch $@ clean_model: diff --git a/compiler/base/__init__.py b/compiler/base/__init__.py index 25f44cf7..6233bf54 100644 --- a/compiler/base/__init__.py +++ b/compiler/base/__init__.py @@ -1,3 +1,8 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# from .channel_route import * from .contact import * from .delay_data import * diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index 7cd1fb53..e4fbdfd8 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import collections -import debug -from tech import drc +from openram import debug +from openram.tech import drc from .vector import vector from .design import design @@ -405,4 +405,3 @@ class channel_route(design): to_layer=self.horizontal_layer, offset=pin_pos) - diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 5f2f41d0..a524c162 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug +from openram.tech import drc, layer, preferred_directions +from openram.tech import layer as tech_layers from .hierarchy_design import hierarchy_design from .vector import vector -from tech import drc, layer, preferred_directions -from tech import layer as tech_layers class contact(hierarchy_design): diff --git a/compiler/base/delay_data.py b/compiler/base/delay_data.py index 9e963265..e53f78fb 100644 --- a/compiler/base/delay_data.py +++ b/compiler/base/delay_data.py @@ -1,12 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - class delay_data(): """ This is the delay class to represent the delay information @@ -38,7 +37,3 @@ class delay_data(): assert isinstance(other, delay_data) return delay_data(other.delay + self.delay, self.slew) - - - - diff --git a/compiler/base/design.py b/compiler/base/design.py index 89f7ba82..0b0228b3 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import GDS, layer -from tech import preferred_directions -from tech import cell_properties as props -from globals import OPTS +from openram import debug +from openram.tech import GDS, layer +from openram.tech import preferred_directions +from openram.tech import cell_properties as props +from openram import OPTS from . import utils from .hierarchy_design import hierarchy_design @@ -67,7 +67,7 @@ class design(hierarchy_design): self.setup_multiport_constants() try: - from tech import power_grid + from openram.tech import power_grid self.supply_stack = power_grid except ImportError: # if no power_grid is specified by tech we use sensible defaults diff --git a/compiler/base/errors.py b/compiler/base/errors.py index e2b9e5ec..557e813f 100644 --- a/compiler/base/errors.py +++ b/compiler/base/errors.py @@ -1,4 +1,8 @@ - +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# class drc_error(Exception): """Exception raised for DRC errors. diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 7451d465..a2687114 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -8,14 +8,14 @@ """ This provides a set of useful generic types for the gdsMill interface. """ -import debug -from .vector import vector -import tech import math import copy import numpy as np -from globals import OPTS +from openram import debug +from openram import tech +from openram import OPTS from .utils import round_to_grid +from .vector import vector class geometry: @@ -249,7 +249,6 @@ class instance(geometry): """ Return an absolute pin that is offset and transformed based on this instance location. Index will return one of several pins.""" - import copy if index == -1: pin = copy.deepcopy(self.mod.get_pin(name)) pin.transform(self.offset, self.mirror, self.rotate) @@ -267,7 +266,6 @@ class instance(geometry): """ Return an absolute pin that is offset and transformed based on this instance location. """ - import copy pin = copy.deepcopy(self.mod.get_pins(name)) new_pins = [] diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index c25864f9..d086d829 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import os +from openram import debug +from openram import OPTS from .hierarchy_layout import layout from .hierarchy_spice import spice -import debug -import os -from globals import OPTS class hierarchy_design(spice, layout): @@ -49,7 +49,7 @@ class hierarchy_design(spice, layout): def DRC_LVS(self, final_verification=False, force_check=False): """Checks both DRC and LVS for a module""" - import verify + from openram import verify # No layout to check if OPTS.netlist_only: @@ -82,7 +82,7 @@ class hierarchy_design(spice, layout): def DRC(self, final_verification=False): """Checks DRC for a module""" - import verify + from openram import verify # Unit tests will check themselves. # Do not run if disabled in options. @@ -102,7 +102,7 @@ class hierarchy_design(spice, layout): def LVS(self, final_verification=False): """Checks LVS for a module""" - import verify + from openram import verify # Unit tests will check themselves. # Do not run if disabled in options. diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index c0da0244..86cf6e43 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1,32 +1,32 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import os import sys +import os import re from math import sqrt -import debug -from gdsMill import gdsMill -import tech -from tech import drc, GDS -from tech import layer as tech_layer -from tech import layer_indices as tech_layer_indices -from tech import preferred_directions -from tech import layer_stacks as tech_layer_stacks -from tech import active_stack as tech_active_stack -from sram_factory import factory -from globals import OPTS +from openram import debug +from openram.gdsMill import gdsMill +from openram import tech +from openram.tech import drc, GDS +from openram.tech import layer as tech_layer +from openram.tech import layer_indices as tech_layer_indices +from openram.tech import preferred_directions +from openram.tech import layer_stacks as tech_layer_stacks +from openram.tech import active_stack as tech_active_stack +from openram.sram_factory import factory +from openram import OPTS from .vector import vector from .pin_layout import pin_layout from .utils import round_to_grid from . import geometry try: - from tech import special_purposes + from openram.tech import special_purposes except ImportError: special_purposes = {} @@ -171,7 +171,7 @@ class layout(): in many places in the compiler. """ try: - from tech import power_grid + from openram.tech import power_grid layout.pwr_grid_layers = [power_grid[0], power_grid[2]] except ImportError: layout.pwr_grid_layers = ["m3", "m4"] @@ -1253,7 +1253,6 @@ class layout(): def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ - from sram_factory import factory via = factory.create(module_type="contact", layer_stack=layers, dimensions=size, @@ -1272,7 +1271,6 @@ class layout(): Add a three layer via structure by the center coordinate accounting for mirroring and rotation. """ - from sram_factory import factory via = factory.create(module_type="contact", layer_stack=layers, dimensions=size, @@ -1379,10 +1377,10 @@ class layout(): def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"): """Adds a ptx module to the design.""" - import ptx - mos = ptx.ptx(width=width, - mults=mults, - tx_type=tx_type) + from openram.modules import ptx + mos = ptx(width=width, + mults=mults, + tx_type=tx_type) inst = self.add_inst(name=mos.name, mod=mos, offset=offset, @@ -2176,7 +2174,6 @@ class layout(): # Find the number of vias for this pitch supply_vias = 1 - from sram_factory import factory while True: c = factory.create(module_type="contact", layer_stack=self.m1_stack, @@ -2289,7 +2286,6 @@ class layout(): # Find the number of vias for this pitch self.supply_vias = 1 - from sram_factory import factory while True: c = factory.create(module_type="contact", layer_stack=self.m1_stack, diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 1216edc5..4beb7c2e 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -1,17 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -import re import os +import re import math -import tech -from globals import OPTS +import textwrap as tr from pprint import pformat +from openram import debug +from openram import tech +from openram import OPTS from .delay_data import delay_data from .wire_spice_model import wire_spice_model from .power_data import power_data @@ -37,7 +38,7 @@ class spice(): # If we have a separate lvs directory, then all the lvs files # should be in there (all or nothing!) try: - from tech import lvs_name + from openram.tech import lvs_name lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/" except ImportError: lvs_dir = OPTS.openram_tech + "lvs_lib/" @@ -338,19 +339,21 @@ class spice(): return # write out the first spice line (the subcircuit) - sp.write("\n.SUBCKT {0} {1}\n".format(self.cell_name, - " ".join(self.pins))) + wrapped_pins = "\n+ ".join(tr.wrap(" ".join(self.pins))) + sp.write("\n.SUBCKT {0}\n+ {1}\n".format(self.cell_name, + wrapped_pins)) # write a PININFO line - pin_info = "*.PININFO" - for pin in self.pins: - if self.pin_type[pin] == "INPUT": - pin_info += " {0}:I".format(pin) - elif self.pin_type[pin] == "OUTPUT": - pin_info += " {0}:O".format(pin) - else: - pin_info += " {0}:B".format(pin) - sp.write(pin_info + "\n") + if False: + pin_info = "*.PININFO" + for pin in self.pins: + if self.pin_type[pin] == "INPUT": + pin_info += " {0}:I".format(pin) + elif self.pin_type[pin] == "OUTPUT": + pin_info += " {0}:O".format(pin) + else: + pin_info += " {0}:B".format(pin) + sp.write(pin_info + "\n") # Also write pins as comments for pin in self.pins: @@ -391,9 +394,11 @@ class spice(): " ".join(self.conns[i]))) sp.write("\n") else: - sp.write("X{0} {1} {2}\n".format(self.insts[i].name, - " ".join(self.conns[i]), - self.insts[i].mod.cell_name)) + wrapped_connections = "\n+ ".join(tr.wrap(" ".join(self.conns[i]))) + + sp.write("X{0}\n+ {1}\n+ {2}\n".format(self.insts[i].name, + wrapped_connections, + self.insts[i].mod.cell_name)) sp.write(".ENDS {0}\n".format(self.cell_name)) @@ -409,6 +414,7 @@ class spice(): sp.write("\n") + def sp_write(self, spname, lvs=False, trim=False): """Writes the spice to files""" debug.info(3, "Writing to {0}".format(spname)) diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 9ebd823d..c8c082ff 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector -from base import pin_layout -from tech import layer_names import os import shutil -from globals import OPTS +from openram import debug +from openram.base import vector +from openram.base import pin_layout +from openram.tech import layer_names +from openram import OPTS class lef: @@ -64,7 +64,7 @@ class lef: f.write('puts "Finished writing LEF cell {}"\n'.format(self.name)) f.close() os.system("chmod u+x {}".format(run_file)) - from run_script import run_script + from openram.verify.run_script import run_script (outfile, errfile, resultsfile) = run_script(self.name, "lef") def lef_write(self, lef_name): diff --git a/compiler/base/logical_effort.py b/compiler/base/logical_effort.py index 15f2b209..971de44f 100644 --- a/compiler/base/logical_effort.py +++ b/compiler/base/logical_effort.py @@ -1,12 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import parameter +from openram import debug +from openram.tech import parameter + class logical_effort(): """ diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index 4021a8b5..d3d92abd 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import GDS, drc -from .vector import vector -from tech import layer, layer_indices import math +from openram import debug +from openram.tech import GDS, drc +from openram.tech import layer, layer_indices +from .vector import vector class pin_layout: @@ -48,8 +48,8 @@ class pin_layout: else: try: - from tech import layer_override - from tech import layer_override_name + from openram.tech import layer_override + from openram.tech import layer_override_name if layer_override[name]: self.lpp = layer_override[name] self.layer = "pwellp" @@ -406,15 +406,15 @@ class pin_layout: # Try to use a global pin purpose if it exists, # otherwise, use the regular purpose try: - from tech import pin_purpose as global_pin_purpose + from openram.tech import pin_purpose as global_pin_purpose pin_purpose = global_pin_purpose except ImportError: pass try: - from tech import label_purpose + from openram.tech import label_purpose try: - from tech import layer_override_purpose + from openram.tech import layer_override_purpose if pin_layer_num in layer_override_purpose: layer_num = layer_override_purpose[pin_layer_num][0] label_purpose = layer_override_purpose[pin_layer_num][1] diff --git a/compiler/base/power_data.py b/compiler/base/power_data.py index 7ab35d14..6e8830f1 100644 --- a/compiler/base/power_data.py +++ b/compiler/base/power_data.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/base/route.py b/compiler/base/route.py index 2a6376e3..3d6ce764 100644 --- a/compiler/base/route.py +++ b/compiler/base/route.py @@ -1,17 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from itertools import tee +from openram import debug +from openram.sram_factory import factory +from openram.tech import drc from .design import design from .vector import vector from .vector3d import vector3d -from tech import drc -from itertools import tee -from sram_factory import factory + class route(design): """ diff --git a/compiler/base/timing_graph.py b/compiler/base/timing_graph.py index 46d7b518..a238cfe0 100644 --- a/compiler/base/timing_graph.py +++ b/compiler/base/timing_graph.py @@ -1,6 +1,11 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# import copy from collections import defaultdict -import debug +from openram import debug class timing_graph(): diff --git a/compiler/base/utils.py b/compiler/base/utils.py index 082caf21..716e208e 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -1,24 +1,22 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. - +# import os import math - -from gdsMill import gdsMill -import tech -import globals -import debug +from openram import debug +from openram import tech +from openram.gdsMill import gdsMill +from openram import OPTS from .vector import vector from .pin_layout import pin_layout try: - from tech import special_purposes + from openram.tech import special_purposes except ImportError: special_purposes = {} -OPTS = globals.OPTS def ceil(decimal): @@ -159,7 +157,7 @@ def get_gds_pins(pin_names, name, gds_filename, units): # may have must-connect pins if isinstance(lpp[1], list): try: - from tech import layer_override + from openram.tech import layer_override if layer_override[pin_name]: lpp = layer_override[pin_name.textString] except: diff --git a/compiler/base/vector.py b/compiler/base/vector.py index 5d011a09..d627729d 100644 --- a/compiler/base/vector.py +++ b/compiler/base/vector.py @@ -1,13 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - import math -import tech +from openram import tech class vector(): diff --git a/compiler/base/vector3d.py b/compiler/base/vector3d.py index 71709837..b1e9a5fe 100644 --- a/compiler/base/vector3d.py +++ b/compiler/base/vector3d.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index b93b52e9..a2e36663 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import math -from tech import spice +from openram.tech import spice class verilog: diff --git a/compiler/base/wire.py b/compiler/base/wire.py index a276c035..d4de4e90 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc +from openram.tech import drc +from openram.sram_factory import factory from .wire_path import wire_path -from sram_factory import factory class wire(wire_path): @@ -71,7 +71,7 @@ class wire(wire_path): # This is here for the unit tests which may not have # initialized the static parts of the layout class yet. - from base import layout + from openram.base import layout layout("fake", "fake") (layer1, via, layer2) = layer_stack diff --git a/compiler/base/wire_path.py b/compiler/base/wire_path.py index 363a41f3..1097c31a 100644 --- a/compiler/base/wire_path.py +++ b/compiler/base/wire_path.py @@ -1,15 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from .vector import vector -from .utils import snap_to_grid +from openram.tech import drc +from openram.tech import layer as techlayer from .design import design -from tech import drc -from tech import layer as techlayer +from .utils import snap_to_grid +from .vector import vector + def create_rectilinear_route(my_list): """ Add intermediate nodes if it isn't rectilinear. Also skip diff --git a/compiler/base/wire_spice_model.py b/compiler/base/wire_spice_model.py index 5e84b64b..341deb23 100644 --- a/compiler/base/wire_spice_model.py +++ b/compiler/base/wire_spice_model.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -16,14 +16,14 @@ class wire_spice_model(): self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment def cal_wire_c(self, wire_length, wire_width): - from tech import spice + from openram.tech import spice # Convert the F/um^2 to fF/um^2 then multiple by width and length total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width wire_c = total_c / self.lump_num return wire_c def cal_wire_r(self, wire_length, wire_width): - from tech import spice + from openram.tech import spice total_r = spice["wire_unit_r"] * wire_length / wire_width wire_r = total_r / self.lump_num return wire_r diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py index c052a0a0..8fba0986 100644 --- a/compiler/characterizer/__init__.py +++ b/compiler/characterizer/__init__.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import os -import debug -from globals import OPTS, find_exe, get_tool +from openram import debug +from openram import OPTS, find_exe, get_tool from .lib import * from .delay import * from .elmore import * @@ -56,4 +56,3 @@ if not OPTS.analytical_delay: else: debug.info(1, "Analytical model enabled.") - diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py index 11e58f73..28ff62ff 100644 --- a/compiler/characterizer/analytical_util.py +++ b/compiler/characterizer/analytical_util.py @@ -1,16 +1,16 @@ +# See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - -import debug - +import os import csv import math import numpy as np -import os +from openram import debug + process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0} diff --git a/compiler/characterizer/bit_polarity.py b/compiler/characterizer/bit_polarity.py index 5b8e5994..94ae478c 100644 --- a/compiler/characterizer/bit_polarity.py +++ b/compiler/characterizer/bit_polarity.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/characterizer/cacti.py b/compiler/characterizer/cacti.py index f1af8fbd..6389f49b 100644 --- a/compiler/characterizer/cacti.py +++ b/compiler/characterizer/cacti.py @@ -1,17 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - -from .simulation import simulation -from globals import OPTS -import debug -import tech - import math +from openram import debug +from openram import tech +from openram import OPTS +from .simulation import simulation + class cacti(simulation): """ diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index 70f80774..c100f365 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import os import re -import debug -from globals import OPTS +from openram import debug +from openram import OPTS def relative_compare(value1, value2, error_tolerance=0.001): diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 8d0aa536..3e7ba3cc 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1,20 +1,20 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import shutil -import debug -import tech import math +import shutil +from openram import debug +from openram import tech +from openram import OPTS from .stimuli import * from .trim_spice import * from .charutils import * from .sram_op import * from .bit_polarity import * -from globals import OPTS from .simulation import simulation from .measurements import * diff --git a/compiler/characterizer/elmore.py b/compiler/characterizer/elmore.py index 5f9eabfd..83000b2a 100644 --- a/compiler/characterizer/elmore.py +++ b/compiler/characterizer/elmore.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - +from openram import debug +from openram import OPTS from .simulation import simulation -from globals import OPTS -import debug + class elmore(simulation): """ diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 0aa9ebcd..40a0ff7f 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -1,18 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import collections -import debug -import random import math +import random +import collections from numpy import binary_repr +from openram import debug +from openram import OPTS from .stimuli import * from .charutils import * -from globals import OPTS from .simulation import simulation diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 8d8674b9..0d75d80f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -1,21 +1,21 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import os,sys,re +import os, sys, re import time -import debug import datetime +import numpy as np +from openram import debug +from openram import tech +from openram.tech import spice +from openram import OPTS from .setup_hold import * from .delay import * from .charutils import * -import tech -import numpy as np -from globals import OPTS -from tech import spice class lib: diff --git a/compiler/characterizer/linear_regression.py b/compiler/characterizer/linear_regression.py index 68921e2c..19904902 100644 --- a/compiler/characterizer/linear_regression.py +++ b/compiler/characterizer/linear_regression.py @@ -1,17 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - -from .regression_model import regression_model from sklearn.linear_model import Ridge -from globals import OPTS -import debug - from sklearn.linear_model import LinearRegression +from openram import debug +from openram import OPTS +from .regression_model import regression_model class linear_regression(regression_model): diff --git a/compiler/characterizer/measurements.py b/compiler/characterizer/measurements.py index fcbb562f..5e7cf2f4 100644 --- a/compiler/characterizer/measurements.py +++ b/compiler/characterizer/measurements.py @@ -1,16 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import drc, parameter, spice from abc import ABC, abstractmethod +from openram import debug +from openram.tech import drc, parameter, spice from .stimuli import * from .charutils import * + class spice_measurement(ABC): """Base class for spice stimulus measurements.""" def __init__(self, measure_name, measure_scale=None, has_port=True): diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py index 9ef48b1c..e2cdc974 100644 --- a/compiler/characterizer/model_check.py +++ b/compiler/characterizer/model_check.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -import tech +from openram import debug +from openram import tech +from openram import OPTS from .stimuli import * from .trim_spice import * from .charutils import * -from globals import OPTS from .delay import delay from .measurements import * diff --git a/compiler/characterizer/neural_network.py b/compiler/characterizer/neural_network.py index ae65b26d..87cfdb58 100644 --- a/compiler/characterizer/neural_network.py +++ b/compiler/characterizer/neural_network.py @@ -1,15 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - -from .regression_model import regression_model -from globals import OPTS -import debug from sklearn.neural_network import MLPRegressor +from openram import debug +from openram import OPTS +from .regression_model import regression_model class neural_network(regression_model): diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index e9b4ec4d..4490cb84 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -1,17 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - +import math +from openram import debug +from openram import OPTS from .analytical_util import * from .simulation import simulation -from globals import OPTS -import debug -import math relative_data_path = "sim_data" data_file = "sim_data.csv" diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index ec1a9e5e..34514604 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import tech +from openram import debug +from openram.sram_factory import factory +from openram import tech +from openram import OPTS from .stimuli import * -import debug from .charutils import * -from globals import OPTS -from sram_factory import factory class setup_hold(): diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 5649099c..80c3103f 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug import math -import tech -from globals import OPTS -from sram_factory import factory -from base import timing_graph +from openram import debug +from openram.base import timing_graph +from openram.sram_factory import factory +from openram import tech +from openram import OPTS class simulation(): diff --git a/compiler/characterizer/sram_op.py b/compiler/characterizer/sram_op.py index e8696347..0339a2a9 100644 --- a/compiler/characterizer/sram_op.py +++ b/compiler/characterizer/sram_op.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b9e4b3c7..7984db58 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -11,12 +11,12 @@ various functions that can be be used to generate stimulus for other simulations as well. """ -import tech -import debug -import subprocess import os +import subprocess import numpy as np -from globals import OPTS +from openram import debug +from openram import tech +from openram import OPTS class stimuli(): diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py index affba296..da2ce2ad 100644 --- a/compiler/characterizer/trim_spice.py +++ b/compiler/characterizer/trim_spice.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from math import log,ceil import re +from math import log, ceil +from openram import debug class trim_spice(): diff --git a/compiler/datasheet/__init__.py b/compiler/datasheet/__init__.py index 369ba8fe..ea4158f6 100644 --- a/compiler/datasheet/__init__.py +++ b/compiler/datasheet/__init__.py @@ -1 +1,6 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# from .datasheet_gen import datasheet_gen diff --git a/compiler/datasheet/add_db.py b/compiler/datasheet/add_db.py index 7d689f4c..6549d2aa 100644 --- a/compiler/datasheet/add_db.py +++ b/compiler/datasheet/add_db.py @@ -1,14 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from pathlib import Path -import glob -import os import sys +import os +import glob +from pathlib import Path + # This is the path to the directory you would like to search # This directory is searched recursively for .html files diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index e7551cd3..5c764316 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from .table_gen import * import os import base64 -from globals import OPTS +from openram import OPTS +from .table_gen import * class datasheet(): diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index f77458b4..11c95ad9 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -15,10 +15,10 @@ a web friendly html datasheet. # Improve css -from globals import OPTS import os import math import csv +from openram import OPTS from .datasheet import datasheet from .table_gen import table_gen diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py index 99e70411..9197b8ba 100644 --- a/compiler/datasheet/table_gen.py +++ b/compiler/datasheet/table_gen.py @@ -1,12 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - class table_gen: """small library of functions to generate the html tables""" diff --git a/compiler/debug.py b/compiler/debug.py index 4052e713..977178d9 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import os -import inspect -import globals import sys +import os import pdb +import inspect +from openram import globals # the debug levels: # 0 = minimum output (default) @@ -96,7 +96,7 @@ log.create_file = True def info(lev, str): - from globals import OPTS + from openram.globals import OPTS # 99 is a special never print level if lev == 99: return @@ -114,7 +114,7 @@ def info(lev, str): def archive(): - from globals import OPTS + from openram.globals import OPTS try: OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) except: @@ -131,7 +131,7 @@ def bp(): An empty function so you can set soft breakpoints in pdb. Usage: 1) Add a breakpoint anywhere in your code with "import debug; debug.bp()". - 2) Run "python3 -m pdb openram.py config.py" or "python3 -m pdb 05_bitcell_array.test" (for example) + 2) Run "python3 -m pdb sram_compiler.py config.py" or "python3 -m pdb 05_bitcell_array.test" (for example) 3) When pdb starts, run "break debug.bp" to set a SOFT breakpoint. (Or you can add this to your ~/.pdbrc) 4) Then run "cont" to continue. 5) You can now set additional breakpoints or display commands diff --git a/compiler/drc/__init__.py b/compiler/drc/__init__.py index 40e3a45c..f9e8d274 100644 --- a/compiler/drc/__init__.py +++ b/compiler/drc/__init__.py @@ -1,3 +1,8 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# from .custom_cell_properties import * from .custom_layer_properties import * from .design_rules import * diff --git a/compiler/drc/custom_cell_properties.py b/compiler/drc/custom_cell_properties.py index 4e7e40e7..45fd589c 100644 --- a/compiler/drc/custom_cell_properties.py +++ b/compiler/drc/custom_cell_properties.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2020 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -186,12 +186,15 @@ class cell_properties(): self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw" self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw" self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw" + self.names["internal"] = "internal" + self.use_strap = False self._ptx = _ptx(model_is_subckt=False, bin_spice_models=False) self._pgate = _pgate(add_implants=False) + self._inv_dec = cell(["A", "Z", "vdd", "gnd"], ["INPUT", "OUTPUT", "POWER", "GROUND"]) @@ -231,6 +234,12 @@ class cell_properties(): self._row_cap_2port = bitcell(["wl0", "wl1", "gnd"], ["INPUT", "INPUT", "POWER", "GROUND"]) + self._internal = cell([],[]) + + @property + def internal(self): + return self._internal + @property def ptx(self): return self._ptx diff --git a/compiler/drc/custom_layer_properties.py b/compiler/drc/custom_layer_properties.py index 8e20d031..9b5872ce 100644 --- a/compiler/drc/custom_layer_properties.py +++ b/compiler/drc/custom_layer_properties.py @@ -1,12 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2020 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - class _bank: def __init__(self, stack, pitch): # bank diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py index dfa23c2a..e4a585f8 100644 --- a/compiler/drc/design_rules.py +++ b/compiler/drc/design_rules.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug from .drc_value import * from .drc_lut import * diff --git a/compiler/drc/drc_lut.py b/compiler/drc/drc_lut.py index e1b36975..3d0aad6d 100644 --- a/compiler/drc/drc_lut.py +++ b/compiler/drc/drc_lut.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug class drc_lut(): diff --git a/compiler/drc/drc_value.py b/compiler/drc/drc_value.py index d4a7cdcc..48c88baf 100644 --- a/compiler/drc/drc_value.py +++ b/compiler/drc/drc_value.py @@ -1,12 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - class drc_value(): """ A single DRC value. diff --git a/compiler/drc/module_type.py b/compiler/drc/module_type.py index 0ffb2eec..02c345d6 100644 --- a/compiler/drc/module_type.py +++ b/compiler/drc/module_type.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/gdsMill/gdsMill/pdfLayout.py b/compiler/gdsMill/gdsMill/pdfLayout.py index a8996f38..71edf3df 100644 --- a/compiler/gdsMill/gdsMill/pdfLayout.py +++ b/compiler/gdsMill/gdsMill/pdfLayout.py @@ -1,8 +1,8 @@ -import pyx import math -from numpy import matrix -from gdsPrimitives import * import random +from numpy import matrix +from openram.gdsMill import pyx +from .gdsPrimitives import * class pdfLayout: """Class representing a view for a layout as a PDF""" diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index 466f4be6..b87aea77 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -1,8 +1,8 @@ -from .gdsPrimitives import * +import math from datetime import * import numpy as np -import math -import debug +from openram import debug +from .gdsPrimitives import * class VlsiLayout: @@ -774,7 +774,7 @@ class VlsiLayout: else: label_text = label.textString try: - from tech import layer_override + from openram.tech import layer_override if layer_override[label_text]: shapes = self.getAllShapes((layer_override[label_text][0], None)) if not shapes: diff --git a/compiler/gen_stimulus.py b/compiler/gen_stimulus.py index 69e53cd8..c0a6c439 100755 --- a/compiler/gen_stimulus.py +++ b/compiler/gen_stimulus.py @@ -1,7 +1,7 @@ #!/usr/bin/env python # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/globals.py b/compiler/globals.py index 9a185052..c66d63ac 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -9,22 +9,22 @@ This is called globals.py, but it actually parses all the arguments and performs the global OpenRAM setup as well. """ +import sys import os -import debug +import re import shutil import optparse -import options -import sys -import re import copy import importlib import getpass import subprocess +from openram import debug +from openram import options VERSION = "1.2.0" NAME = "OpenRAM v{}".format(VERSION) -USAGE = "openram.py [options] \nUse -h for help.\n" +USAGE = "sram_compiler.py [options] \nUse -h for help.\n" OPTS = options.options() CHECKPOINT_OPTS = None @@ -141,9 +141,6 @@ def print_banner(): debug.print_raw("|=========" + user_info.center(60) + "=========|") dev_info = "Development help: openram-dev-group@ucsc.edu" debug.print_raw("|=========" + dev_info.center(60) + "=========|") - if OPTS.openram_temp: - temp_info = "Temp dir: {}".format(OPTS.openram_temp) - debug.print_raw("|=========" + temp_info.center(60) + "=========|") debug.print_raw("|=========" + "See LICENSE for license info".center(60) + "=========|") debug.print_raw("|==============================================================================|") @@ -188,7 +185,7 @@ def check_versions(): OPTS.coverage = 0 -def init_openram(config_file, is_unit_test=True): +def init_openram(config_file, is_unit_test=False): """ Initialize the technology, paths, simulators, etc. """ check_versions() @@ -205,7 +202,7 @@ def init_openram(config_file, is_unit_test=True): init_paths() - from sram_factory import factory + from openram.sram_factory import factory factory.reset() global OPTS @@ -225,8 +222,8 @@ def init_openram(config_file, is_unit_test=True): setup_bitcell() # Import these to find the executables for checkpointing - import characterizer - import verify + from openram import characterizer + from openram import verify # Make a checkpoint of the options so we can restore # after each unit test if not CHECKPOINT_OPTS: @@ -252,7 +249,7 @@ def setup_bitcell(): # See if bitcell exists try: - c = importlib.import_module("modules." + OPTS.bitcell) + c = importlib.import_module("openram.modules." + OPTS.bitcell) mod = getattr(c, OPTS.bitcell) except ImportError: # Use the pbitcell if we couldn't find a custom bitcell @@ -297,7 +294,7 @@ def get_tool(tool_type, preferences, default_name=None): return(None, "") -def read_config(config_file, is_unit_test=True): +def read_config(config_file, is_unit_test=False): """ Read the configuration file that defines a few parameters. The config file is just a Python file that defines some config @@ -388,7 +385,7 @@ def end_openram(): cleanup_paths() if OPTS.check_lvsdrc: - import verify + from openram import verify verify.print_drc_stats() verify.print_lvs_stats() verify.print_pex_stats() @@ -432,16 +429,8 @@ def setup_paths(): global OPTS - try: - OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - except: - debug.error("$OPENRAM_HOME is not properly defined.", 1) - - debug.check(os.path.isdir(OPENRAM_HOME), - "$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME)) - - if OPENRAM_HOME not in sys.path: - debug.error("Please add OPENRAM_HOME to the PYTHONPATH.", -1) + from openram import OPENRAM_HOME + debug.info(1, "OpenRAM source code found in {}".format(OPENRAM_HOME)) # Use a unique temp subdirectory if multithreaded if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp": @@ -511,7 +500,7 @@ def init_paths(): def set_default_corner(): """ Set the default corner. """ - import tech + from openram import tech # Set some default options now based on the technology... if (OPTS.process_corners == ""): if OPTS.nominal_corner_only: @@ -544,14 +533,32 @@ def import_tech(): """ Dynamically adds the tech directory to the path and imports it. """ global OPTS - debug.info(2, - "Importing technology: " + OPTS.tech_name) + debug.info(2, "Importing technology: " + OPTS.tech_name) - # environment variable should point to the technology dir + OPENRAM_TECH = "" + + # Check if $OPENRAM_TECH is defined try: OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH")) except: - debug.error("$OPENRAM_TECH environment variable is not defined.", 1) + debug.info(2, + "$OPENRAM_TECH environment variable is not defined. " + "Only the default technology modules will be considered if installed.") + # Point to the default technology modules that are part of the openram package + try: + import openram + if OPENRAM_TECH != "": + OPENRAM_TECH += ":" + OPENRAM_TECH += os.path.dirname(openram.__file__) + "/technology" + except: + if OPENRAM_TECH == "": + debug.warning("Couldn't find a tech directory. " + "Install openram library or set $OPENRAM_TECH.") + + debug.info(1, "Tech directory found in {}".format(OPENRAM_TECH)) + + # Add this environment variable to os.environ + os.environ["OPENRAM_TECH"] = OPENRAM_TECH # Add all of the paths for tech_path in OPENRAM_TECH.split(":"): @@ -568,18 +575,23 @@ def import_tech(): OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/" - # Prepend the tech directory so it is sourced FIRST + # Append tech_path to openram.__path__ to import it from openram tech_path = OPTS.openram_tech - sys.path.insert(0, tech_path) + openram.__path__.append(tech_path) try: - import tech + from openram import tech except ImportError: debug.error("Could not load tech module.", -1) - # Prepend custom modules of the technology to the path, if they exist - custom_mod_path = os.path.join(tech_path, "modules/") + # Remove OPENRAM_TECH from sys.path because we should be done with those + for tech_path in OPENRAM_TECH.split(":"): + sys.path.remove(tech_path) + + # Add the custom modules to "tech" + custom_mod_path = os.path.join(tech_path, "custom/") if os.path.exists(custom_mod_path): - sys.path.insert(0, custom_mod_path) + from openram import tech + tech.__path__.append(custom_mod_path) def print_time(name, now_time, last_time=None, indentation=2): diff --git a/compiler/model_configs/shared_config.py b/compiler/model_configs/shared_config.py index 6faa9fda..265781ab 100644 --- a/compiler/model_configs/shared_config.py +++ b/compiler/model_configs/shared_config.py @@ -1 +1,6 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# model_name = "cacti" diff --git a/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py b/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py index cb95031c..7e92d7c6 100644 --- a/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py +++ b/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 10 num_words = 64 words_per_row = 4 diff --git a/compiler/model_configs/sram_128b_1024_1rw.py b/compiler/model_configs/sram_128b_1024_1rw.py index dcefd390..df4d06e9 100644 --- a/compiler/model_configs/sram_128b_1024_1rw.py +++ b/compiler/model_configs/sram_128b_1024_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 128 num_words = 1024 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py b/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py index a3920fe2..e6c4d793 100644 --- a/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py +++ b/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 12 num_words = 128 words_per_row = 4 diff --git a/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py b/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py index 1d10601b..c4aa4aed 100644 --- a/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py +++ b/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 12 num_words = 16 words_per_row = 1 diff --git a/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py b/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py index 8cb43861..5b8dca44 100644 --- a/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py +++ b/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 12 num_words = 256 words_per_row = 16 diff --git a/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py b/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py index 7f09eb55..09c8beda 100644 --- a/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py +++ b/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 12 num_words = 256 words_per_row = 8 diff --git a/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py b/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py index c57fb0f5..53ad1b52 100644 --- a/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py +++ b/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 14 num_words = 32 words_per_row = 2 diff --git a/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py b/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py index b27f609f..047e5bc9 100644 --- a/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py +++ b/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 15 num_words = 512 words_per_row = 8 diff --git a/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py b/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py index 63fd918d..8a510c05 100644 --- a/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py +++ b/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 16 num_words = 1024 words_per_row = 16 diff --git a/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py b/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py index 9a1ab061..5628ebf0 100644 --- a/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py +++ b/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 17 num_words = 1024 words_per_row = 16 diff --git a/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py b/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py index d0479f51..fc48955c 100644 --- a/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py +++ b/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 17 num_words = 256 words_per_row = 16 diff --git a/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py b/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py index 65382903..04ea9c3e 100644 --- a/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py +++ b/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 18 num_words = 128 words_per_row = 2 diff --git a/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py b/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py index c0d73dfb..279599c0 100644 --- a/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py +++ b/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 18 num_words = 32 words_per_row = 1 diff --git a/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py b/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py index 5f831189..2b421716 100644 --- a/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py +++ b/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 21 num_words = 1024 words_per_row = 4 diff --git a/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py b/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py index cbb02b50..b6bb4211 100644 --- a/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py +++ b/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 22 num_words = 512 words_per_row = 16 diff --git a/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py b/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py index 1d7227b4..485722fc 100644 --- a/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py +++ b/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 23 num_words = 1024 words_per_row = 16 diff --git a/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py b/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py index a8160a1a..766c5135 100644 --- a/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py +++ b/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 26 num_words = 64 words_per_row = 4 diff --git a/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py b/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py index 34c3c56a..59465de2 100644 --- a/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py +++ b/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 27 num_words = 1024 words_per_row = 4 diff --git a/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py b/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py index 816f8139..f21c7745 100644 --- a/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py +++ b/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 27 num_words = 256 words_per_row = 8 diff --git a/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py b/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py index eec58a67..9faf9de3 100644 --- a/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py +++ b/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 27 num_words = 512 words_per_row = 4 diff --git a/compiler/model_configs/sram_32b_1024_1rw.py b/compiler/model_configs/sram_32b_1024_1rw.py index 9bef6fc6..181261fe 100644 --- a/compiler/model_configs/sram_32b_1024_1rw.py +++ b/compiler/model_configs/sram_32b_1024_1rw.py @@ -1,3 +1,8 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# from shared_config import * word_size = 32 num_words = 1024 @@ -5,4 +10,4 @@ num_words = 1024 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_32b_2048_1rw.py b/compiler/model_configs/sram_32b_2048_1rw.py index f7c18aff..ee4112b9 100644 --- a/compiler/model_configs/sram_32b_2048_1rw.py +++ b/compiler/model_configs/sram_32b_2048_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 32 num_words = 2048 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_32b_256_1rw.py b/compiler/model_configs/sram_32b_256_1rw.py index 998d1db1..6c4600ab 100644 --- a/compiler/model_configs/sram_32b_256_1rw.py +++ b/compiler/model_configs/sram_32b_256_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 32 num_words = 256 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py b/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py index 89a61e1d..2d6d9e53 100644 --- a/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py +++ b/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 32 num_words = 32 words_per_row = 1 diff --git a/compiler/model_configs/sram_32b_512_1rw.py b/compiler/model_configs/sram_32b_512_1rw.py index 24bab462..8601b267 100644 --- a/compiler/model_configs/sram_32b_512_1rw.py +++ b/compiler/model_configs/sram_32b_512_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 32 num_words = 512 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py b/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py index eabc5206..237191ea 100644 --- a/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py +++ b/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 4 num_words = 16 words_per_row = 1 diff --git a/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py b/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py index e7f5bea2..e881a167 100644 --- a/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py +++ b/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 4 num_words = 32 words_per_row = 2 diff --git a/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py b/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py index f85ad51b..6efe1625 100644 --- a/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py +++ b/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 4 num_words = 64 words_per_row = 4 diff --git a/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py b/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py index 49277e05..512907e2 100644 --- a/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py +++ b/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 5 num_words = 256 words_per_row = 16 diff --git a/compiler/model_configs/sram_64b_1024_1rw.py b/compiler/model_configs/sram_64b_1024_1rw.py index 35130d96..8e91ea1a 100644 --- a/compiler/model_configs/sram_64b_1024_1rw.py +++ b/compiler/model_configs/sram_64b_1024_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 64 num_words = 1024 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_64b_512_1rw.py b/compiler/model_configs/sram_64b_512_1rw.py index 4511604e..7cb2c495 100644 --- a/compiler/model_configs/sram_64b_512_1rw.py +++ b/compiler/model_configs/sram_64b_512_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 64 num_words = 512 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py b/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py index 0460c6a9..49a103c0 100644 --- a/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py +++ b/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 6 num_words = 16 words_per_row = 1 diff --git a/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py b/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py index 3cf12e6e..a0f03291 100644 --- a/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py +++ b/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 7 num_words = 256 words_per_row = 4 diff --git a/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py b/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py index 008e928f..b1b1d384 100644 --- a/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py +++ b/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 7 num_words = 64 words_per_row = 2 diff --git a/compiler/model_configs/sram_8b_1024_1rw.py b/compiler/model_configs/sram_8b_1024_1rw.py index aed46407..a57ebc25 100644 --- a/compiler/model_configs/sram_8b_1024_1rw.py +++ b/compiler/model_configs/sram_8b_1024_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 8 num_words = 1024 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_8b_256_1rw.py b/compiler/model_configs/sram_8b_256_1rw.py index 7c77ce6c..d23d3475 100644 --- a/compiler/model_configs/sram_8b_256_1rw.py +++ b/compiler/model_configs/sram_8b_256_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 8 num_words = 256 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py b/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py index 3d34aae7..9a27487b 100644 --- a/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py +++ b/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 8 num_words = 256 words_per_row = 1 diff --git a/compiler/model_configs/sram_8b_512_1rw.py b/compiler/model_configs/sram_8b_512_1rw.py index f3c5b8fd..a61c2279 100644 --- a/compiler/model_configs/sram_8b_512_1rw.py +++ b/compiler/model_configs/sram_8b_512_1rw.py @@ -1,8 +1,13 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 8 num_words = 512 output_extended_config = True output_datasheet_info = True netlist_only = True -nominal_corner_only = True \ No newline at end of file +nominal_corner_only = True diff --git a/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py b/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py index a0a8f76a..af102882 100644 --- a/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py +++ b/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 9 num_words = 1024 words_per_row = 4 diff --git a/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py b/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py index 9122ceaa..64fb0655 100644 --- a/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py +++ b/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 9 num_words = 128 words_per_row = 1 diff --git a/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py b/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py index 9a0da00b..485e4048 100644 --- a/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py +++ b/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py @@ -1,4 +1,9 @@ -from shared_config import * +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +from .shared_config import * word_size = 9 num_words = 256 words_per_row = 4 diff --git a/compiler/model_data_util.py b/compiler/model_data_util.py index 9cf6db7b..785a00a3 100644 --- a/compiler/model_data_util.py +++ b/compiler/model_data_util.py @@ -1,3 +1,8 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# import os import csv import re @@ -266,4 +271,4 @@ if __name__ == "__main__": else: input_dir_path = sys.argv[1] out_path = sys.argv[2] - gen_model_csv(input_dir_path, out_path) \ No newline at end of file + gen_model_csv(input_dir_path, out_path) diff --git a/compiler/modules/__init__.py b/compiler/modules/__init__.py old mode 100644 new mode 100755 index b2f78ba7..5d10d3fa --- a/compiler/modules/__init__.py +++ b/compiler/modules/__init__.py @@ -1,3 +1,8 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# from .and2_dec import * from .and3_dec import * from .and4_dec import * @@ -78,5 +83,4 @@ from .write_driver_array import * from .write_driver import * from .write_mask_and_array import * from .sram_1bank import * -from .sram_config import * -from .sram import * +from .internal_base import * diff --git a/compiler/modules/and2_dec.py b/compiler/modules/and2_dec.py index 8ce10caa..3371a84e 100644 --- a/compiler/modules/and2_dec.py +++ b/compiler/modules/and2_dec.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector -from base import design -from sram_factory import factory -from globals import OPTS -from tech import layer +from openram import debug +from openram.base import vector +from openram.base import design +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS class and2_dec(design): diff --git a/compiler/modules/and3_dec.py b/compiler/modules/and3_dec.py index 9c8ee348..96155751 100644 --- a/compiler/modules/and3_dec.py +++ b/compiler/modules/and3_dec.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from sram_factory import factory -from globals import OPTS -from tech import layer +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS class and3_dec(design): diff --git a/compiler/modules/and4_dec.py b/compiler/modules/and4_dec.py index 6d75eedd..7ef88dbc 100644 --- a/compiler/modules/and4_dec.py +++ b/compiler/modules/and4_dec.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from sram_factory import factory -from globals import OPTS -from tech import layer +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS class and4_dec(design): diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c9279d2a..5e50f1f1 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1,18 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from sram_factory import factory from math import log, ceil, floor -from tech import drc -from globals import OPTS -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc +from openram.tech import layer_properties as layer_props +from openram import OPTS class bank(design): diff --git a/compiler/modules/bitcell_1port.py b/compiler/modules/bitcell_1port.py index 57943697..613b4551 100644 --- a/compiler/modules/bitcell_1port.py +++ b/compiler/modules/bitcell_1port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base @@ -29,7 +29,3 @@ class bitcell_1port(bitcell_base): """ self.add_graph_edges(graph, port_nets) - def is_non_inverting(self): - """Return input to output polarity for module""" - - return False diff --git a/compiler/modules/bitcell_2port.py b/compiler/modules/bitcell_2port.py index 716c79b7..1f1b26f1 100644 --- a/compiler/modules/bitcell_2port.py +++ b/compiler/modules/bitcell_2port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base @@ -99,8 +99,3 @@ class bitcell_2port(bitcell_base): # Port 1 edges graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) - - def is_non_inverting(self): - """Return input to output polarity for module""" - - return False diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index e50c5b73..93297331 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug +from openram.tech import drc, spice +from openram.sram_factory import factory +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from tech import drc, spice -from globals import OPTS -from sram_factory import factory class bitcell_array(bitcell_base_array): diff --git a/compiler/modules/bitcell_base.py b/compiler/modules/bitcell_base.py index 25d3efe4..5866d8e9 100644 --- a/compiler/modules/bitcell_base.py +++ b/compiler/modules/bitcell_base.py @@ -1,16 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - -import debug -from base import design -from globals import OPTS -from base import logical_effort -from tech import parameter, drc, layer, spice +from openram import debug +from openram.base import design +from openram.base import logical_effort +from openram.tech import parameter, drc, layer, spice +from openram import OPTS class bitcell_base(design): @@ -46,7 +45,7 @@ class bitcell_base(design): def analytical_power(self, corner, load): """Bitcell power in nW. Only characterizes leakage.""" - from tech import spice + from openram.tech import spice leakage = spice["bitcell_leakage"] # FIXME dynamic = 0 @@ -265,3 +264,15 @@ class bitcell_base(design): delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m) return delay + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + debug.error("Must override build_graph function in bitcell base class.") + + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 00a80abc..080dc565 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from sram_factory import factory -from globals import OPTS +from openram import debug +from openram.base import design +from openram.sram_factory import factory +from openram import OPTS class bitcell_base_array(design): diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 158cf04b..afd6dfd6 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +from openram.sram_factory import factory +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from sram_factory import factory -from globals import OPTS class col_cap_array(bitcell_base_array): diff --git a/compiler/modules/col_cap_bitcell_1port.py b/compiler/modules/col_cap_bitcell_1port.py index 35331779..6ab7e72e 100644 --- a/compiler/modules/col_cap_bitcell_1port.py +++ b/compiler/modules/col_cap_bitcell_1port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base diff --git a/compiler/modules/col_cap_bitcell_2port.py b/compiler/modules/col_cap_bitcell_2port.py index 6e5cffa7..803d8409 100644 --- a/compiler/modules/col_cap_bitcell_2port.py +++ b/compiler/modules/col_cap_bitcell_2port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base diff --git a/compiler/modules/column_decoder.py b/compiler/modules/column_decoder.py index 2c7199b8..bfd772e5 100644 --- a/compiler/modules/column_decoder.py +++ b/compiler/modules/column_decoder.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2022 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # -from tech import drc -import debug -from base import design import math -from sram_factory import factory -from base import vector -from globals import OPTS -from tech import cell_properties -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc +from openram.tech import cell_properties +from openram.tech import layer_properties as layer_props +from openram import OPTS class column_decoder(design): diff --git a/compiler/modules/column_mux.py b/compiler/modules/column_mux.py index 67c44894..824e21a7 100644 --- a/compiler/modules/column_mux.py +++ b/compiler/modules/column_mux.py @@ -1,18 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc, layer +from openram.tech import cell_properties as cell_props +from openram import OPTS from .pgate import * -import debug -from tech import drc, layer -from base import vector -from .pgate import * -from sram_factory import factory -from tech import cell_properties as cell_props -from globals import OPTS class column_mux(pgate): diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py index b8aae4a5..d3490c6b 100644 --- a/compiler/modules/column_mux_array.py +++ b/compiler/modules/column_mux_array.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug -from tech import layer, preferred_directions -from base import vector -from sram_factory import factory -from globals import OPTS -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer, preferred_directions +from openram.tech import layer_properties as layer_props +from openram import OPTS class column_mux_array(design): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 7d265c9c..b9904ee5 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from sram_factory import factory import math -from base import vector -from globals import OPTS +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS from .control_logic_base import control_logic_base diff --git a/compiler/modules/control_logic_base.py b/compiler/modules/control_logic_base.py index decf1f50..f8a42dd9 100644 --- a/compiler/modules/control_logic_base.py +++ b/compiler/modules/control_logic_base.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug -from sram_factory import factory import math -from base import vector -from globals import OPTS -from base import logical_effort +from openram import debug +from openram.base import design +from openram.base import logical_effort +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class control_logic_base(design): diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index c393e280..e2bbea51 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class delay_chain(design): diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 0f7cb777..c328a1da 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from tech import cell_properties as props -from tech import spice +from openram.base import design +from openram.tech import cell_properties as props +from openram.tech import spice class dff(design): diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 5a9070c7..9bc43813 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from sram_factory import factory -from globals import OPTS +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class dff_array(design): diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index b0cd619c..df7ca8b8 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from tech import layer -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS class dff_buf(design): diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index e284b589..5cd8fd9c 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class dff_buf_array(design): diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 4d162c23..3f36ab00 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class dff_inv(design): diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 97cbd590..dc01b91b 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class dff_inv_array(design): diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 566122e7..06f23ef7 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +from openram.sram_factory import factory +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from sram_factory import factory -from globals import OPTS class dummy_array(bitcell_base_array): diff --git a/compiler/modules/dummy_bitcell_1port.py b/compiler/modules/dummy_bitcell_1port.py index 3c6f9da6..1556b80c 100644 --- a/compiler/modules/dummy_bitcell_1port.py +++ b/compiler/modules/dummy_bitcell_1port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base @@ -21,4 +21,6 @@ class dummy_bitcell_1port(bitcell_base): super().__init__(name, prop=props.bitcell_1port) debug.info(2, "Create dummy bitcell") - + def build_graph(self, graph, inst_name, port_nets): + """ Adds edges based on inputs/outputs. Overrides base class function. """ + pass diff --git a/compiler/modules/dummy_bitcell_2port.py b/compiler/modules/dummy_bitcell_2port.py index 94f99f39..af868062 100644 --- a/compiler/modules/dummy_bitcell_2port.py +++ b/compiler/modules/dummy_bitcell_2port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base @@ -21,4 +21,6 @@ class dummy_bitcell_2port(bitcell_base): super().__init__(name, prop=props.bitcell_2port) debug.info(2, "Create dummy bitcell 2 port object") - + def build_graph(self, graph, inst_name, port_nets): + """ Adds edges based on inputs/outputs. Overrides base class function. """ + pass diff --git a/compiler/modules/dummy_pbitcell.py b/compiler/modules/dummy_pbitcell.py index 7b099218..0eea9944 100644 --- a/compiler/modules/dummy_pbitcell.py +++ b/compiler/modules/dummy_pbitcell.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class dummy_pbitcell(design): diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index b25c37de..ed579e14 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from .bitcell_base_array import bitcell_base_array -from globals import OPTS -from sram_factory import factory -from base import vector -import debug from numpy import cumsum -from tech import layer_properties as layer_props +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer_properties as layer_props +from openram import OPTS +from .bitcell_base_array import bitcell_base_array class global_bitcell_array(bitcell_base_array): diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 3d3c3087..3cf6903b 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -1,20 +1,21 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design import math -from sram_factory import factory -from base import vector -from globals import OPTS -from tech import layer_indices -from tech import layer_stacks -from tech import layer_properties as layer_props -from tech import drc +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer_indices +from openram.tech import layer_stacks +from openram.tech import layer_properties as layer_props +from openram.tech import drc +from openram import OPTS + class hierarchical_decoder(design): """ diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 867b113b..c5f5255d 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -1,21 +1,21 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design import math -from base import vector -from sram_factory import factory -from globals import OPTS -from tech import layer_properties as layer_props -from tech import layer_indices -from tech import layer_stacks -from tech import preferred_directions -from tech import drc +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer_properties as layer_props +from openram.tech import layer_indices +from openram.tech import layer_stacks +from openram.tech import preferred_directions +from openram.tech import drc +from openram import OPTS class hierarchical_predecode(design): diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index bdd01499..2c6a7d50 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import OPTS from .hierarchical_predecode import hierarchical_predecode -from globals import OPTS class hierarchical_predecode2x4(hierarchical_predecode): diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index dc8e026c..88aaa401 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import OPTS from .hierarchical_predecode import hierarchical_predecode -from globals import OPTS class hierarchical_predecode3x8(hierarchical_predecode): diff --git a/compiler/modules/hierarchical_predecode4x16.py b/compiler/modules/hierarchical_predecode4x16.py index 7227bf3b..71a2765a 100644 --- a/compiler/modules/hierarchical_predecode4x16.py +++ b/compiler/modules/hierarchical_predecode4x16.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import OPTS from .hierarchical_predecode import hierarchical_predecode -from globals import OPTS class hierarchical_predecode4x16(hierarchical_predecode): diff --git a/compiler/modules/internal_base.py b/compiler/modules/internal_base.py new file mode 100755 index 00000000..8c11ab51 --- /dev/null +++ b/compiler/modules/internal_base.py @@ -0,0 +1,14 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +from openram.base import design + + +class internal_base(design): + + def __init__(self, name, cell_name=None, prop=None): + design.__init__(self, name, cell_name, prop) diff --git a/compiler/modules/inv_dec.py b/compiler/modules/inv_dec.py index 8f143e29..1af8ae5c 100644 --- a/compiler/modules/inv_dec.py +++ b/compiler/modules/inv_dec.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from base import logical_effort -from tech import cell_properties as props -from tech import spice, parameter +from openram.base import design +from openram.base import logical_effort +from openram.tech import cell_properties as props +from openram.tech import spice, parameter class inv_dec(design): diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 8104e1d2..30defe29 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer_properties as layer_props +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from globals import OPTS -from sram_factory import factory -from base import vector -import debug -from tech import layer_properties as layer_props class local_bitcell_array(bitcell_base_array): diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index e5c4bbfc..418e40a7 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -1,19 +1,20 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import sys -from tech import drc, parameter -import debug -from base import design import math -from math import log,sqrt,ceil -from base import vector -from sram_factory import factory -from globals import OPTS +from math import log, sqrt, ceil +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc, parameter +from openram import OPTS + class multibank(design): """ diff --git a/compiler/modules/nand2_dec.py b/compiler/modules/nand2_dec.py index c21ac384..1a92e46c 100644 --- a/compiler/modules/nand2_dec.py +++ b/compiler/modules/nand2_dec.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from tech import spice, parameter, drc -from tech import cell_properties as props -from base import logical_effort +from openram.base import design +from openram.base import logical_effort +from openram.tech import spice, parameter, drc +from openram.tech import cell_properties as props class nand2_dec(design): diff --git a/compiler/modules/nand3_dec.py b/compiler/modules/nand3_dec.py index 78b6724f..9ced188a 100644 --- a/compiler/modules/nand3_dec.py +++ b/compiler/modules/nand3_dec.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from tech import spice, parameter, drc -from tech import cell_properties as props -from base import logical_effort +from openram.base import design +from openram.base import logical_effort +from openram.tech import spice, parameter, drc +from openram.tech import cell_properties as props class nand3_dec(design): diff --git a/compiler/modules/nand4_dec.py b/compiler/modules/nand4_dec.py index f4d507de..826e432d 100644 --- a/compiler/modules/nand4_dec.py +++ b/compiler/modules/nand4_dec.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from tech import spice, parameter, drc -from tech import cell_properties as props -from base import logical_effort +from openram.base import design +from openram.base import logical_effort +from openram.tech import spice, parameter, drc +from openram.tech import cell_properties as props class nand4_dec(design): diff --git a/compiler/modules/orig_bitcell_array.py b/compiler/modules/orig_bitcell_array.py index 2e3088af..7973ece5 100644 --- a/compiler/modules/orig_bitcell_array.py +++ b/compiler/modules/orig_bitcell_array.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram.sram_factory import factory +from openram.tech import drc, spice +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from tech import drc, spice -from globals import OPTS -from sram_factory import factory class bitcell_array(bitcell_base_array): diff --git a/compiler/modules/pand2.py b/compiler/modules/pand2.py index 8bd17589..4055bd7d 100644 --- a/compiler/modules/pand2.py +++ b/compiler/modules/pand2.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector +from openram import debug +from openram.base import vector +from openram.sram_factory import factory from .pgate import * -from sram_factory import factory class pand2(pgate): diff --git a/compiler/modules/pand3.py b/compiler/modules/pand3.py index f63b8c41..820e5b19 100644 --- a/compiler/modules/pand3.py +++ b/compiler/modules/pand3.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector +from openram import debug +from openram.base import vector +from openram.sram_factory import factory from .pgate import * -from sram_factory import factory class pand3(pgate): diff --git a/compiler/modules/pand4.py b/compiler/modules/pand4.py index 9b5a31d6..6fbfee10 100644 --- a/compiler/modules/pand4.py +++ b/compiler/modules/pand4.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector +from openram import debug +from openram.base import vector +from openram.sram_factory import factory from .pgate import * -from sram_factory import factory class pand4(pgate): diff --git a/compiler/modules/pbitcell.py b/compiler/modules/pbitcell.py index 516dca3f..60ffb454 100644 --- a/compiler/modules/pbitcell.py +++ b/compiler/modules/pbitcell.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import logical_effort -from base import vector -from tech import drc, parameter, layer -from tech import cell_properties as props -from globals import OPTS +from openram import debug +from openram.base import logical_effort +from openram.base import vector +from openram.tech import drc, parameter, layer +from openram.tech import cell_properties as props +from openram import OPTS from .ptx import ptx from .bitcell_base import bitcell_base diff --git a/compiler/modules/pbuf.py b/compiler/modules/pbuf.py index ba44fe2f..2a5e665d 100644 --- a/compiler/modules/pbuf.py +++ b/compiler/modules/pbuf.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector +from openram import debug +from openram.base import vector +from openram.sram_factory import factory from .pgate import * -from sram_factory import factory class pbuf(pgate): diff --git a/compiler/modules/pbuf_dec.py b/compiler/modules/pbuf_dec.py index c04d4922..eecb7ed5 100644 --- a/compiler/modules/pbuf_dec.py +++ b/compiler/modules/pbuf_dec.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector +from openram import debug +from openram.base import vector +from openram.sram_factory import factory from .pgate import * -from sram_factory import factory class pbuf_dec(pgate): diff --git a/compiler/modules/pdriver.py b/compiler/modules/pdriver.py index a9241af5..9dadf360 100644 --- a/compiler/modules/pdriver.py +++ b/compiler/modules/pdriver.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug +from openram.base import vector +from openram.sram_factory import factory from .pgate import * -from base import vector -from sram_factory import factory class pdriver(pgate): diff --git a/compiler/modules/pgate.py b/compiler/modules/pgate.py index 0ddbc48e..02f58dbc 100644 --- a/compiler/modules/pgate.py +++ b/compiler/modules/pgate.py @@ -1,21 +1,21 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from base import vector -import debug import math from bisect import bisect_left -from tech import layer, drc -from globals import OPTS -from tech import cell_properties as cell_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.tech import layer, drc +from openram.tech import cell_properties as cell_props +from openram import OPTS if cell_props.ptx.bin_spice_models: - from tech import nmos_bins, pmos_bins + from openram.tech import nmos_bins, pmos_bins class pgate(design): diff --git a/compiler/modules/pinv.py b/compiler/modules/pinv.py index a60bed13..4c16f029 100644 --- a/compiler/modules/pinv.py +++ b/compiler/modules/pinv.py @@ -1,22 +1,22 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from .pgate import * -from base import vector -from base import logical_effort -from base.utils import round_to_grid -from base.errors import drc_error import operator -from tech import drc, parameter, spice from math import ceil -from globals import OPTS -from sram_factory import factory -from tech import cell_properties as cell_props +from openram import debug +from openram.base import vector +from openram.base import logical_effort +from openram.base.utils import round_to_grid +from openram.base.errors import drc_error +from openram.sram_factory import factory +from openram.tech import drc, parameter, spice +from openram.tech import cell_properties as cell_props +from openram import OPTS +from .pgate import * class pinv(pgate): diff --git a/compiler/modules/pinv_dec.py b/compiler/modules/pinv_dec.py index 7b378f08..fd10663a 100644 --- a/compiler/modules/pinv_dec.py +++ b/compiler/modules/pinv_dec.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc, parameter, layer +from openram.tech import cell_properties as cell_props +from openram import OPTS from .pinv import pinv -from tech import drc, parameter, layer -from globals import OPTS -from sram_factory import factory -from tech import cell_properties as cell_props class pinv_dec(pinv): diff --git a/compiler/modules/pinvbuf.py b/compiler/modules/pinvbuf.py index 78dca7b5..c6c9e274 100644 --- a/compiler/modules/pinvbuf.py +++ b/compiler/modules/pinvbuf.py @@ -1,15 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer from .pgate import * -from base import vector -from sram_factory import factory -from tech import layer + class pinvbuf(pgate): """ diff --git a/compiler/modules/pnand2.py b/compiler/modules/pnand2.py index 9262b2f8..6ac97059 100644 --- a/compiler/modules/pnand2.py +++ b/compiler/modules/pnand2.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.base import logical_effort +from openram.sram_factory import factory +from openram.tech import drc, parameter, spice +from openram.tech import cell_properties as cell_props from .pgate import * -import debug -from tech import drc, parameter, spice -from base import vector -from base import logical_effort -from sram_factory import factory -from tech import cell_properties as cell_props class pnand2(pgate): diff --git a/compiler/modules/pnand3.py b/compiler/modules/pnand3.py index 31a1b400..70e57723 100644 --- a/compiler/modules/pnand3.py +++ b/compiler/modules/pnand3.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.base import logical_effort +from openram.sram_factory import factory +from openram.tech import drc, parameter, spice +from openram.tech import cell_properties as cell_props from .pgate import * -import debug -from tech import drc, parameter, spice -from base import vector -from base import logical_effort -from sram_factory import factory -from tech import cell_properties as cell_props class pnand3(pgate): diff --git a/compiler/modules/pnand4.py b/compiler/modules/pnand4.py index db0cbf96..dde8e3d0 100644 --- a/compiler/modules/pnand4.py +++ b/compiler/modules/pnand4.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.base import logical_effort +from openram.sram_factory import factory +from openram.tech import drc, parameter, spice +from openram.tech import cell_properties as cell_props from .pgate import * -import debug -from tech import drc, parameter, spice -from base import vector -from base import logical_effort -from sram_factory import factory -from tech import cell_properties as cell_props class pnand4(pgate): diff --git a/compiler/modules/pnor2.py b/compiler/modules/pnor2.py index 35df000f..d33a6e7b 100644 --- a/compiler/modules/pnor2.py +++ b/compiler/modules/pnor2.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc, parameter, spice +from openram.tech import cell_properties as cell_props from .pgate import * -import debug -from tech import drc, parameter, spice -from base import vector -from sram_factory import factory -from tech import cell_properties as cell_props class pnor2(pgate): diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 576dff01..630ef3a7 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # from math import log, ceil -import debug -from base import design -from sram_factory import factory -from base import vector -from tech import layer, drc -from globals import OPTS -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer, drc +from openram.tech import layer_properties as layer_props +from openram import OPTS class port_address(design): diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index f34aa893..3ad224c3 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -1,18 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # -from tech import drc -import debug -from base import design import math -from sram_factory import factory from collections import namedtuple -from base import vector -from globals import OPTS -from tech import cell_properties -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc +from openram.tech import cell_properties +from openram.tech import layer_properties as layer_props +from openram import OPTS class port_data(design): diff --git a/compiler/modules/precharge.py b/compiler/modules/precharge.py index 4a1267e5..eb6f967f 100644 --- a/compiler/modules/precharge.py +++ b/compiler/modules/precharge.py @@ -1,18 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import parameter, drc +from openram.tech import cell_properties as cell_props +from openram import OPTS from .pgate import * -from tech import parameter, drc -from base import vector -from globals import OPTS -from sram_factory import factory -from tech import cell_properties as cell_props class precharge(design): diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 3c7ab681..75db792e 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug -from base import vector -from sram_factory import factory -from globals import OPTS +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class precharge_array(design): diff --git a/compiler/modules/ptristate_inv.py b/compiler/modules/ptristate_inv.py index 583b68ea..b69e3026 100644 --- a/compiler/modules/ptristate_inv.py +++ b/compiler/modules/ptristate_inv.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc, parameter, spice from .pgate import * -import debug -from tech import drc, parameter, spice -from base import vector -from sram_factory import factory class ptristate_inv(pgate): diff --git a/compiler/modules/ptx.py b/compiler/modules/ptx.py index d1bd13c8..462c6491 100644 --- a/compiler/modules/ptx.py +++ b/compiler/modules/ptx.py @@ -1,18 +1,18 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import logical_effort -from base import vector -from tech import layer, drc, spice -from sram_factory import factory -from globals import OPTS -from tech import cell_properties as cell_props +from openram import debug +from openram.base import design +from openram.base import logical_effort +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer, drc, spice +from openram.tech import cell_properties as cell_props +from openram import OPTS class ptx(design): diff --git a/compiler/modules/pwrite_driver.py b/compiler/modules/pwrite_driver.py index 9af6c78f..27859d82 100644 --- a/compiler/modules/pwrite_driver.py +++ b/compiler/modules/pwrite_driver.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -#Copyright (c) 2021 Regents of the University of California and The Board -#of Regents for the Oklahoma Agricultural and Mechanical College -#(acting for and on behalf of Oklahoma State University) -#All rights reserved. +# Copyright (c) 2016-2022 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. # -from base import design -from tech import parameter -import debug -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import parameter +from openram import OPTS class pwrite_driver(design): diff --git a/compiler/modules/replica_bitcell_1port.py b/compiler/modules/replica_bitcell_1port.py index f4c9432e..ca79c797 100644 --- a/compiler/modules/replica_bitcell_1port.py +++ b/compiler/modules/replica_bitcell_1port.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug +from openram.base import logical_effort +from openram.tech import cell_properties as props +from openram.tech import parameter, drc from .bitcell_base import bitcell_base -from tech import cell_properties as props -from tech import parameter, drc -from base import logical_effort class replica_bitcell_1port(bitcell_base): @@ -39,7 +39,7 @@ class replica_bitcell_1port(bitcell_base): def analytical_power(self, corner, load): """Bitcell power in nW. Only characterizes leakage.""" - from tech import spice + from openram.tech import spice leakage = spice["bitcell_leakage"] dynamic = 0 # FIXME total_power = self.return_power(dynamic, leakage) diff --git a/compiler/modules/replica_bitcell_2port.py b/compiler/modules/replica_bitcell_2port.py index eb46f6d0..34a5df4e 100644 --- a/compiler/modules/replica_bitcell_2port.py +++ b/compiler/modules/replica_bitcell_2port.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug +from openram import debug +from openram.base import logical_effort +from openram.tech import cell_properties as props +from openram.tech import parameter, drc from .bitcell_base import bitcell_base -from tech import cell_properties as props -from tech import parameter, drc -from base import logical_effort class replica_bitcell_2port(bitcell_base): diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 07cbc405..d78181fe 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -1,17 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # - -import debug -from base import vector -from base import contact +from openram import debug +from openram.base import vector +from openram.base import contact +from openram.sram_factory import factory +from openram.tech import drc, spice +from openram.tech import cell_properties as props +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from tech import drc, spice -from tech import cell_properties as props -from globals import OPTS -from sram_factory import factory class replica_bitcell_array(bitcell_base_array): diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 04072eab..2424b20e 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # -import debug +from openram import debug +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer_properties as layer_props +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from sram_factory import factory -from base import vector -from globals import OPTS -from tech import layer_properties as layer_props class replica_column(bitcell_base_array): diff --git a/compiler/modules/replica_pbitcell.py b/compiler/modules/replica_pbitcell.py index 54fda10a..ad1afb4e 100644 --- a/compiler/modules/replica_pbitcell.py +++ b/compiler/modules/replica_pbitcell.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class replica_pbitcell(design): diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index 61b736b3..12d5dba8 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +from openram.sram_factory import factory +from openram import OPTS from .bitcell_base_array import bitcell_base_array -from sram_factory import factory -from globals import OPTS class row_cap_array(bitcell_base_array): diff --git a/compiler/modules/row_cap_bitcell_1port.py b/compiler/modules/row_cap_bitcell_1port.py index d9defc1b..639c6584 100644 --- a/compiler/modules/row_cap_bitcell_1port.py +++ b/compiler/modules/row_cap_bitcell_1port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base diff --git a/compiler/modules/row_cap_bitcell_2port.py b/compiler/modules/row_cap_bitcell_2port.py index 2f6bf766..44b116ef 100644 --- a/compiler/modules/row_cap_bitcell_2port.py +++ b/compiler/modules/row_cap_bitcell_2port.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import cell_properties as props +from openram import debug +from openram.tech import cell_properties as props from .bitcell_base import bitcell_base diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index e90a02ca..a2d75c47 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug -from tech import parameter, drc, spice -from tech import cell_properties as props -from base import logical_effort +from openram import debug +from openram.base import design +from openram.base import logical_effort +from openram.tech import parameter, drc, spice +from openram.tech import cell_properties as props class sense_amp(design): @@ -43,7 +43,7 @@ class sense_amp(design): # FIXME: This input load will be applied to both the s_en timing and bitline timing. # Input load for the bitlines which are connected to the source/drain of a TX. Not the selects. - from tech import spice + from openram.tech import spice # Default is 8x. Per Samira and Hodges-Jackson book: # "Column-mux transistors driven by the decoder must be sized for optimal speed" bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file. diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 3e98a517..a15cc6d9 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -from base import vector -from sram_factory import factory -from tech import cell_properties -import debug -from globals import OPTS +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import cell_properties +from openram import OPTS class sense_amp_array(design): diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 63303c40..9004a4b6 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -1,23 +1,23 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import vector -from base import channel_route -from router import router_tech -from globals import OPTS, print_time import datetime -import debug from math import ceil -from importlib import reload -from base import design -from base import verilog -from base import lef -from sram_factory import factory -from tech import spice +from importlib import import_module, reload +from openram import debug +from openram.base import vector +from openram.base import channel_route +from openram.base import design +from openram.base import verilog +from openram.base import lef +from openram.router import router_tech +from openram.sram_factory import factory +from openram.tech import spice +from openram import OPTS, print_time class sram_1bank(design, verilog, lef): @@ -43,7 +43,7 @@ class sram_1bank(design, verilog, lef): self.num_spare_cols = 0 try: - from tech import power_grid + from openram.tech import power_grid self.supply_stack = power_grid except ImportError: # if no power_grid is specified by tech we use sensible defaults @@ -254,9 +254,9 @@ class sram_1bank(design, verilog, lef): # Do not route the power supply (leave as must-connect pins) return elif OPTS.route_supplies == "grid": - from router import supply_grid_router as router + from openram.router import supply_grid_router as router else: - from router import supply_tree_router as router + from openram.router import supply_tree_router as router rtr=router(layers=self.supply_stack, design=self, bbox=bbox, @@ -367,7 +367,7 @@ class sram_1bank(design, verilog, lef): for bit in range(self.num_spare_cols): pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) - from router import signal_escape_router as router + from openram.router import signal_escape_router as router rtr=router(layers=self.m3_stack, design=self, bbox=bbox) @@ -482,7 +482,7 @@ class sram_1bank(design, verilog, lef): self.bank_count = 0 - c = reload(__import__('modules.' + OPTS.control_logic)) + c = reload(import_module("." + OPTS.control_logic, "openram.modules")) self.mod_control_logic = getattr(c, OPTS.control_logic) # Create the control logic module for each port type diff --git a/compiler/modules/sram_multibank.py b/compiler/modules/sram_multibank.py index 675e0c02..05a62187 100644 --- a/compiler/modules/sram_multibank.py +++ b/compiler/modules/sram_multibank.py @@ -1,8 +1,13 @@ -from .template import template -from globals import OPTS +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# import os -from math import ceil, log import re +from math import ceil, log +from openram import OPTS +from .template import template class sram_multibank: diff --git a/compiler/modules/template.py b/compiler/modules/template.py index ae93647f..18650874 100644 --- a/compiler/modules/template.py +++ b/compiler/modules/template.py @@ -1,7 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California -# Santa Cruz +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # import re diff --git a/compiler/modules/tri_gate.py b/compiler/modules/tri_gate.py index c5d65d57..f5d18434 100644 --- a/compiler/modules/tri_gate.py +++ b/compiler/modules/tri_gate.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from tech import spice +from openram import debug +from openram.base import design +from openram.tech import spice class tri_gate(design): diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index 984d8039..92841dc2 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from tech import drc -from base import design -from base import vector -from sram_factory import factory -from globals import OPTS +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc +from openram import OPTS class tri_gate_array(design): """ diff --git a/compiler/modules/wordline_buffer_array.py b/compiler/modules/wordline_buffer_array.py index d624d5db..c2e17864 100644 --- a/compiler/modules/wordline_buffer_array.py +++ b/compiler/modules/wordline_buffer_array.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from tech import layer -from base import vector -from sram_factory import factory -from globals import OPTS -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import layer +from openram.tech import layer_properties as layer_props +from openram import OPTS class wordline_buffer_array(design): diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index e8fd8901..b9c81990 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import vector -from base import design -from sram_factory import factory -from globals import OPTS -from tech import layer -from tech import layer_properties as layer_props +from openram import debug +from openram.base import vector +from openram.base import design +from openram.sram_factory import factory +from openram.tech import layer +from openram.tech import layer_properties as layer_props +from openram import OPTS class wordline_driver(design): diff --git a/compiler/modules/wordline_driver_array.py b/compiler/modules/wordline_driver_array.py index f88d6b86..522a90e5 100644 --- a/compiler/modules/wordline_driver_array.py +++ b/compiler/modules/wordline_driver_array.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from tech import drc, layer -from base import vector -from sram_factory import factory -from globals import OPTS -from tech import layer_properties as layer_props +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc, layer +from openram.tech import layer_properties as layer_props +from openram import OPTS class wordline_driver_array(design): diff --git a/compiler/modules/write_driver.py b/compiler/modules/write_driver.py index 00afa0ee..1ff8f1c1 100644 --- a/compiler/modules/write_driver.py +++ b/compiler/modules/write_driver.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from tech import cell_properties as props +from openram import debug +from openram.base import design +from openram.tech import cell_properties as props class write_driver(design): diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 5c3b664f..ef94877a 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -1,17 +1,17 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug import math -from tech import drc -from sram_factory import factory -from base import vector -from globals import OPTS +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram.tech import drc +from openram import OPTS class write_driver_array(design): diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index f3e7e9bc..21d364f0 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -1,16 +1,16 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug import math -from sram_factory import factory -from base import vector -from globals import OPTS +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class write_mask_and_array(design): diff --git a/compiler/options.py b/compiler/options.py index 770045b3..6939ab76 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -1,19 +1,19 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import optparse import os +import optparse class options(optparse.Values): """ Class for holding all of the OpenRAM options. All of these options can be over-riden in a configuration file - that is the sole required command-line positional argument for openram.py. + that is the sole required command-line positional argument for sram_compiler.py. """ ################### diff --git a/compiler/printGDS.py b/compiler/printGDS.py deleted file mode 100755 index 6472dd7e..00000000 --- a/compiler/printGDS.py +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/env python3 - -import sys -from gdsMill import gdsMill - -if len(sys.argv) < 2: - print("Usage: {0} file.gds".format(sys.argv[0])) - sys.exit(1) - -gds_file = sys.argv[1] -arrayCellLayout = gdsMill.VlsiLayout() -reader = gdsMill.Gds2reader(arrayCellLayout,debugToTerminal = 1) -reader.loadFromFile(gds_file) - diff --git a/compiler/processGDS.py b/compiler/processGDS.py deleted file mode 100755 index 1fb0a024..00000000 --- a/compiler/processGDS.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 - -import sys -from gdsMill import gdsMill - -if len(sys.argv) < 2: - print("Usage: {0} in.gds out.gds".format(sys.argv[0])) - sys.exit(1) - -in_gds_file = sys.argv[1] -out_gds_file = sys.argv[2] -layout = gdsMill.VlsiLayout() -reader = gdsMill.Gds2reader(layout) -reader.loadFromFile(in_gds_file) - - -struct = layout.structures[layout.rootStructureName] -# Do something to the structure -for text in struct.texts: - print(text.textString) - text.magFactor="" - -writer = gdsMill.Gds2writer(layout) -writer.writeToFile(out_gds_file) - diff --git a/compiler/router/__init__.py b/compiler/router/__init__.py index a4496fb0..71beb2a2 100644 --- a/compiler/router/__init__.py +++ b/compiler/router/__init__.py @@ -1,3 +1,8 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# from .router import * from .signal_escape_router import * from .signal_router import * diff --git a/compiler/router/direction.py b/compiler/router/direction.py index a7eeb727..2f84d297 100644 --- a/compiler/router/direction.py +++ b/compiler/router/direction.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # from enum import Enum -from base.vector3d import vector3d -import debug +from openram import debug +from openram.base.vector3d import vector3d class direction(Enum): diff --git a/compiler/router/grid.py b/compiler/router/grid.py index 1ace0e05..18538b27 100644 --- a/compiler/router/grid.py +++ b/compiler/router/grid.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base.vector3d import vector3d +from openram import debug +from openram.base.vector3d import vector3d from .grid_cell import grid_cell diff --git a/compiler/router/grid_cell.py b/compiler/router/grid_cell.py index 7c3ee51f..ac0abbdb 100644 --- a/compiler/router/grid_cell.py +++ b/compiler/router/grid_cell.py @@ -1,10 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # + class grid_cell: """ A single cell that can be occupied in a given layer, blocked, diff --git a/compiler/router/grid_path.py b/compiler/router/grid_path.py index 1c7c576a..8ca4478d 100644 --- a/compiler/router/grid_path.py +++ b/compiler/router/grid_path.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # from itertools import tee -from base.vector3d import vector3d +from openram.base.vector3d import vector3d from .grid import grid from .direction import direction diff --git a/compiler/router/grid_utils.py b/compiler/router/grid_utils.py index 0bf954a3..564200bf 100644 --- a/compiler/router/grid_utils.py +++ b/compiler/router/grid_utils.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -10,8 +10,8 @@ Some utility functions for sets of grid cells. """ import math +from openram.base.vector3d import vector3d from .direction import direction -from base.vector3d import vector3d def increment_set(curset, direct): diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 7d7f25d8..a1cd328d 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base.vector import vector -from base.vector3d import vector3d -from base.pin_layout import pin_layout +from openram import debug +from openram.base.vector import vector +from openram.base.vector3d import vector3d +from openram.base.pin_layout import pin_layout from .direction import direction diff --git a/compiler/router/router.py b/compiler/router/router.py index 2e18b37a..3699351b 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -1,22 +1,21 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - -import itertools import math +import itertools from datetime import datetime -from gdsMill import gdsMill -import debug -from globals import OPTS, print_time -from tech import drc, GDS -from tech import layer as techlayer -from base.vector import vector -from base.vector3d import vector3d -from base.pin_layout import pin_layout +from openram import debug +from openram.base.vector import vector +from openram.base.vector3d import vector3d +from openram.base.pin_layout import pin_layout +from openram.gdsMill import gdsMill +from openram.tech import drc, GDS +from openram.tech import layer as techlayer +from openram import OPTS, print_time from .router_tech import router_tech from .pin_group import pin_group from . import grid_utils diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py index 22f1fd15..098a9af3 100644 --- a/compiler/router/router_tech.py +++ b/compiler/router/router_tech.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc, layer, preferred_directions -from base.contact import contact -from base.vector import vector -import debug import math +from openram import debug +from openram.base.contact import contact +from openram.base.vector import vector +from openram.tech import drc, layer, preferred_directions class router_tech: diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py index a1d1e10a..56cbb921 100644 --- a/compiler/router/signal_escape_router.py +++ b/compiler/router/signal_escape_router.py @@ -1,13 +1,13 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # from datetime import datetime -import debug -from globals import print_time +from openram import debug +from openram import print_time from .router import router from .signal_grid import signal_grid diff --git a/compiler/router/signal_grid.py b/compiler/router/signal_grid.py index f6ea31f5..6ffc7304 100644 --- a/compiler/router/signal_grid.py +++ b/compiler/router/signal_grid.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from heapq import heappush,heappop from copy import deepcopy -from base.vector3d import vector3d +from heapq import heappush,heappop +from openram import debug +from openram.base.vector3d import vector3d from .grid import grid from .grid_path import grid_path diff --git a/compiler/router/signal_router.py b/compiler/router/signal_router.py index 11e40a91..9c984bdb 100644 --- a/compiler/router/signal_router.py +++ b/compiler/router/signal_router.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from router import router +from openram import debug +from openram.router import router class signal_router(router): diff --git a/compiler/router/supply_grid.py b/compiler/router/supply_grid.py index 9ebe58a0..fdf8fc76 100644 --- a/compiler/router/supply_grid.py +++ b/compiler/router/supply_grid.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index 24cd168f..b7c3d7a2 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # from datetime import datetime -import debug -from globals import print_time -from base.vector3d import vector3d +from openram import debug +from openram.base.vector3d import vector3d +from openram import print_time from .router import router from .direction import direction from .supply_grid import supply_grid diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index a34f7dd0..eafdac5d 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -8,8 +8,8 @@ from datetime import datetime from scipy.sparse import csr_matrix from scipy.sparse.csgraph import minimum_spanning_tree -import debug -from globals import print_time +from openram import debug +from openram import print_time from .router import router from . import grid_utils from .signal_grid import signal_grid diff --git a/compiler/modules/sram.py b/compiler/sram.py similarity index 84% rename from compiler/modules/sram.py rename to compiler/sram.py index 6c26e5ec..66c4c955 100644 --- a/compiler/modules/sram.py +++ b/compiler/sram.py @@ -1,32 +1,45 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import datetime import os -import debug -from characterizer import functional -from globals import OPTS, print_time import shutil +import datetime +from openram import debug +from openram import sram_config as config +from openram import OPTS, print_time class sram(): """ This is not a design module, but contains an SRAM design instance. - It could later try options of number of banks and oganization to compare + It could later try options of number of banks and organization to compare results. We can later add visualizer and other high-level functions as needed. """ - def __init__(self, sram_config, name): + def __init__(self, sram_config=None, name=None): + + # Create default configs if custom config isn't provided + if sram_config is None: + sram_config = config(word_size=OPTS.word_size, + num_words=OPTS.num_words, + write_size=OPTS.write_size, + num_banks=OPTS.num_banks, + words_per_row=OPTS.words_per_row, + num_spare_rows=OPTS.num_spare_rows, + num_spare_cols=OPTS.num_spare_cols) + + if name is None: + name = OPTS.output_name sram_config.set_local_config(self) # reset the static duplicate name checker for unit tests # in case we create more than one SRAM - from base import design + from openram.base import design design.name_map=[] debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size, @@ -36,7 +49,7 @@ class sram(): self.name = name - from .sram_1bank import sram_1bank as sram + from openram.modules.sram_1bank import sram_1bank as sram self.s = sram(name, sram_config) @@ -59,7 +72,7 @@ class sram(): def verilog_write(self, name): self.s.verilog_write(name) if self.num_banks != 1: - from .sram_multibank import sram_multibank + from openram.modules.sram_multibank import sram_multibank mb = sram_multibank(self.s) mb.verilog_write(name[:-2] + '_top.v') @@ -80,7 +93,8 @@ class sram(): # Import this at the last minute so that the proper tech file # is loaded and the right tools are selected - import verify + from openram import verify + from openram.characterizer import functional # Save the spice file start_time = datetime.datetime.now() @@ -144,7 +158,7 @@ class sram(): # Characterize the design start_time = datetime.datetime.now() - from characterizer import lib + from openram.characterizer import lib debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) @@ -158,7 +172,7 @@ class sram(): # Write the datasheet start_time = datetime.datetime.now() - from datasheet import datasheet_gen + from openram.datasheet import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) diff --git a/compiler/modules/sram_config.py b/compiler/sram_config.py similarity index 96% rename from compiler/modules/sram_config.py rename to compiler/sram_config.py index a46c80a2..119dfaca 100644 --- a/compiler/modules/sram_config.py +++ b/compiler/sram_config.py @@ -1,14 +1,14 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug from math import log, sqrt, ceil -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_config: @@ -28,12 +28,12 @@ class sram_config: self.num_spare_cols = num_spare_cols try: - from tech import array_row_multiple + from openram.tech import array_row_multiple self.array_row_multiple = array_row_multiple except ImportError: self.array_row_multiple = 1 try: - from tech import array_col_multiple + from openram.tech import array_col_multiple self.array_col_multiple = array_col_multiple except ImportError: self.array_col_multiple = 1 diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 0ebb6865..fae33f38 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from globals import OPTS import importlib +from openram import OPTS class sram_factory: @@ -39,7 +39,7 @@ class sram_factory: """ overridden = False try: - from tech import tech_modules + from openram.tech import tech_modules real_module_type = tech_modules[module_type] # If we are given a list of modules, it is indexed by number of ports starting from 1 if type(real_module_type) is list: @@ -105,12 +105,14 @@ class sram_factory: try: # Dynamically load the module if real_module_type == "contact": - c = importlib.import_module("base.contact") + c = importlib.import_module("openram.base.contact") + elif real_module_type == "sram": + c = importlib.import_module("openram.sram") else: - c = importlib.import_module("modules."+real_module_type) + c = importlib.import_module("openram.modules."+real_module_type) except ModuleNotFoundError: # Check if it is a technology specific module - c = importlib.import_module("custom."+real_module_type) + c = importlib.import_module("openram.custom."+real_module_type) mod = getattr(c, real_module_type) diff --git a/compiler/tests/00_code_format_check_test.py b/compiler/tests/00_code_format_check_test.py index cfe72a21..30cdeac6 100755 --- a/compiler/tests/00_code_format_check_test.py +++ b/compiler/tests/00_code_format_check_test.py @@ -1,18 +1,18 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # - +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -import debug +import openram +from openram import debug + class code_format_test(openram_test): "Run a test to check for tabs instead of spaces in the all source files." @@ -30,12 +30,13 @@ class code_format_test(openram_test): errors += check_file_format_carriage(code) errors += check_file_format_whitespace(code) + # Check for "print" for code in source_codes: if re.search("gdsMill", code): continue if re.search("debug.py$", code): continue - if re.search("openram.py$", code): + if re.search("sram_compiler.py$", code): continue if re.search("testutils.py$", code): continue @@ -43,6 +44,11 @@ class code_format_test(openram_test): continue errors += check_print_output(code) + # Check for copyright + for code in source_codes: + if re.search("gdsMill", code): + continue + errors += check_copyright(code) # fails if there are any tabs in any files self.assertEqual(errors, 0) @@ -145,9 +151,42 @@ def check_print_output(file_name): return(count) +def check_copyright(file_name): + """ Check if any file doesn't contain the copyright at the top. """ + + from datetime import date + year = date.today().year + old_copyright = ("# See LICENSE for licensing information.\n" + "#\n" + "# Copyright (c) 2016-{} Regents of the University of California and The Board\n" + "# of Regents for the Oklahoma Agricultural and Mechanical College\n" + "# (acting for and on behalf of Oklahoma State University)\n" + "# All rights reserved.\n" + "#\n").format(year) + new_copyright = ("# See LICENSE for licensing information.\n" + "#\n" + "# Copyright (c) 2016-{} Regents of the University of California, Santa Cruz\n" + "# All rights reserved.\n" + "#\n").format(year) + skip_files = [] + base_file_name = os.path.basename(file_name) + if base_file_name in skip_files: + return 0 + file = open(file_name, "r") + line = file.read() + file.close() + # Skip possible shebang at the top + line = re.sub(r'#!.*\n', '', line) + # Check if copyright is missing + if not line.startswith(old_copyright) and not line.startswith(new_copyright): + debug.info(0, "\nFound missing/wrong copyright in " + file_name) + return 1 + return 0 + + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/01_library_test.py b/compiler/tests/01_library_test.py index 03a7f1f3..2229a04e 100755 --- a/compiler/tests/01_library_test.py +++ b/compiler/tests/01_library_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + class library_lvs_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import verify + openram.init_openram(config_file, is_unit_test=True) + from openram import verify (gds_dir, sp_dir, allnames) = setup_files() drc_errors = 0 @@ -41,7 +42,7 @@ class library_lvs_test(openram_test): # fail if the error count is not zero self.assertEqual(drc_errors + lvs_errors, 0) - globals.end_openram() + openram.end_openram() def setup_files(): @@ -66,7 +67,7 @@ def setup_files(): tempnames[i] = re.sub('\.sp$', '', tempnames[i]) try: - from tech import blackbox_cells + from openram.tech import blackbox_cells nameset = list(set(tempnames) - set(blackbox_cells)) except ImportError: # remove duplicate base names @@ -78,7 +79,7 @@ def setup_files(): # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 34c96063..3dd2d6e5 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -1,27 +1,28 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class contact_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) - from tech import active_stack, poly_stack, beol_stacks + from openram.tech import active_stack, poly_stack, beol_stacks # Don't do active because of nwell contact rules # Don't do metal3 because of min area rules @@ -86,13 +87,12 @@ class contact_test(openram_test): well_type="p") self.local_drc_check(c) - globals.end_openram() - + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index a08edad7..046de020 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -1,27 +1,28 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + class path_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from base import wire_path - import tech - from base import design + openram.init_openram(config_file, is_unit_test=True) + from openram.base import wire_path + from openram import tech + from openram.base import design min_space = 2 * tech.drc["minwidth_m1"] layer_stack = ("m1") @@ -86,13 +87,12 @@ class path_test(openram_test): wire_path(w, layer_stack, position_list) self.local_drc_check(w) - globals.end_openram() - + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 2ebf7d45..790ef3f1 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class ptx_1finger_nmos_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking min size NMOS with 1 finger") fet = factory.create(module_type="ptx", @@ -30,12 +30,12 @@ class ptx_1finger_nmos_test(openram_test): tx_type="nmos") self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 53922c9b..de146f3b 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class ptx_1finger_pmos_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking min size PMOS with 1 finger") fet = factory.create(module_type="ptx", @@ -29,12 +30,12 @@ class ptx_1finger_pmos_test(openram_test): tx_type="pmos") self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index a4e18aa2..a6b2ca55 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class ptx_3finger_nmos_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking three fingers NMOS") fet = factory.create(module_type="ptx", @@ -32,12 +33,12 @@ class ptx_3finger_nmos_test(openram_test): connect_poly=True) self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index b4776456..acbf1ea9 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class ptx_3finger_pmos_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking three fingers PMOS") fet = factory.create(module_type="ptx", @@ -32,12 +33,12 @@ class ptx_3finger_pmos_test(openram_test): connect_poly=True) self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index c1c2184b..1bed7938 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class ptx_4finger_nmos_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking three fingers NMOS") fet = factory.create(module_type="ptx", @@ -32,12 +33,12 @@ class ptx_4finger_nmos_test(openram_test): connect_poly=True) self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index fcc843bb..15634d71 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class ptx_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking three fingers PMOS") fet = factory.create(module_type="ptx", @@ -32,12 +33,12 @@ class ptx_test(openram_test): connect_poly=True) self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_ptx_no_contacts_test.py b/compiler/tests/03_ptx_no_contacts_test.py index 36b53d8f..a665d1f5 100755 --- a/compiler/tests/03_ptx_no_contacts_test.py +++ b/compiler/tests/03_ptx_no_contacts_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class ptx_no_contacts_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import tech + openram.init_openram(config_file, is_unit_test=True) + from openram import tech debug.info(2, "Checking single finger no source/drain") fet = factory.create(module_type="ptx", @@ -49,12 +49,12 @@ class ptx_no_contacts_test(openram_test): tx_type="nmos") self.local_drc_check(fet) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 8906e1cf..08a0c8eb 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -1,27 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys -import os -import globals +import openram class wire_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from base import wire - import tech - from base import design + openram.init_openram(config_file, is_unit_test=True) + from openram.base import wire + from openram import tech + from openram.base import design layer_stacks = [tech.poly_stack] + tech.beol_stacks @@ -50,12 +49,12 @@ class wire_test(openram_test): wire(w, layer_stack, position_list) self.local_drc_check(w) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py index 93ad6d41..04ff56ad 100755 --- a/compiler/tests/04_and2_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class and2_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - global verify - import verify + openram.init_openram(config_file, is_unit_test=True) + #global verify + from openram import verify OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing and2_dec 1rw/1r gate") a = factory.create(module_type="and2_dec") @@ -36,17 +36,18 @@ class and2_dec_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing and2_dec 1rw gate") a = factory.create(module_type="and2_dec") self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py index 6b6389e3..d7db7aba 100755 --- a/compiler/tests/04_and3_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class and3_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - global verify - import verify + openram.init_openram(config_file, is_unit_test=True) + #global verify + from openram import verify OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing and3_dec 1rw/1r gate") a = factory.create(module_type="and3_dec") @@ -36,17 +36,18 @@ class and3_dec_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing and3_dec 1rw gate") a = factory.create(module_type="and3_dec") self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index c849e6d6..7e79cfaf 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS # @unittest.skip("SKIPPING 04_and4_dec_test") @@ -21,14 +21,14 @@ class and4_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - global verify - import verify + openram.init_openram(config_file, is_unit_test=True) + #global verify + from openram import verify OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing and4_dec 1rw/1r gate") a = factory.create(module_type="and4_dec") @@ -37,17 +37,18 @@ class and4_dec_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing and4_dec 1rw gate") a = factory.create(module_type="and4_dec") self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_column_mux_1rw_1r_test.py b/compiler/tests/04_column_mux_1rw_1r_test.py index 56b4301a..3844a62a 100755 --- a/compiler/tests/04_column_mux_1rw_1r_test.py +++ b/compiler/tests/04_column_mux_1rw_1r_test.py @@ -1,31 +1,31 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Checking column mux port 0") tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") @@ -35,11 +35,12 @@ class column_mux_1rw_1r_test(openram_test): tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_column_mux_pbitcell_test.py b/compiler/tests/04_column_mux_pbitcell_test.py index 4ce02164..61016df3 100755 --- a/compiler/tests/04_column_mux_pbitcell_test.py +++ b/compiler/tests/04_column_mux_pbitcell_test.py @@ -1,26 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check single level column mux in multi-port OPTS.bitcell = "pbitcell" @@ -38,11 +38,12 @@ class column_mux_pbitcell_test(openram_test): tx = factory.create(module_type="column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_column_mux_test.py b/compiler/tests/04_column_mux_test.py index 78770b5b..b016d6b3 100755 --- a/compiler/tests/04_column_mux_test.py +++ b/compiler/tests/04_column_mux_test.py @@ -1,37 +1,38 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check single level column mux in single port debug.info(2, "Checking column mux") tx = factory.create(module_type="column_mux", tx_size=8) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_dff_buf_test.py b/compiler/tests/04_dff_buf_test.py index c8d2842e..7ce74904 100755 --- a/compiler/tests/04_dff_buf_test.py +++ b/compiler/tests/04_dff_buf_test.py @@ -1,35 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class dff_buf_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index 0d955283..006c1ca5 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class replica_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import dummy_pbitcell + openram.init_openram(config_file, is_unit_test=True) + from openram.modules import dummy_pbitcell OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 @@ -41,11 +42,12 @@ class replica_pbitcell_test(openram_test): tx = dummy_pbitcell(name="rpbc") self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index d1e9f6ff..89527388 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -1,39 +1,40 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS class pand2_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - global verify - import verify + openram.init_openram(config_file, is_unit_test=True) + #global verify + from openram import verify - from modules import pand2 + from openram.modules import pand2 debug.info(2, "Testing pand2 gate 4x") a = pand2(name="pand2x4", size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index 3b49e3a1..3f6044fa 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -1,39 +1,40 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS class pand3_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - global verify - import verify + openram.init_openram(config_file, is_unit_test=True) + #global verify + from openram import verify - from modules import pand3 + from openram.modules import pand3 debug.info(2, "Testing pand3 gate 4x") a = pand3(name="pand3x4", size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pand4_test.py b/compiler/tests/04_pand4_test.py index 2c5f5878..80865017 100755 --- a/compiler/tests/04_pand4_test.py +++ b/compiler/tests/04_pand4_test.py @@ -1,39 +1,40 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS class pand4_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - global verify - import verify + openram.init_openram(config_file, is_unit_test=True) + #global verify + from openram import verify - from modules import pand4 + from openram.modules import pand4 debug.info(2, "Testing pand4 gate 4x") a = pand4(name="pand4x4", size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 119afc41..ec3e77d5 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug -from sram_factory import factory +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + #@unittest.skip("SKIPPING 04_pbitcell_test") class pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 @@ -102,13 +103,12 @@ class pbitcell_test(openram_test): tx = factory.create(module_type="pbitcell") self.local_check(tx) - globals.end_openram() - + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pbuf_dec_8x_test.py b/compiler/tests/04_pbuf_dec_8x_test.py index 823f9bcc..976d4c77 100755 --- a/compiler/tests/04_pbuf_dec_8x_test.py +++ b/compiler/tests/04_pbuf_dec_8x_test.py @@ -1,40 +1,42 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pbuf_dec_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Checking 8x size decoder buffer") a = factory.create(module_type="pbuf_dec", size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 72a5f2ff..e1b0fe01 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pbuf_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing buffer 8x") a = factory.create(module_type="pbuf", size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index 71ad80cd..2de65e0b 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pdriver_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions @@ -41,11 +42,12 @@ class pdriver_test(openram_test): f = factory.create(module_type="pdriver", fanout = 64, inverting = True) self.local_check(f) - globals.end_openram() + openram.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_100x_test.py b/compiler/tests/04_pinv_100x_test.py index 0d86e0a8..d4de539d 100755 --- a/compiler/tests/04_pinv_100x_test.py +++ b/compiler/tests/04_pinv_100x_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 100x inverter") tx = factory.create(module_type="pinv", size=100) self.local_check(tx) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 8151bf41..188c37e9 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) self.local_check(tx) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 9ecbc3aa..2e067ef0 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index f6f4ca04..8295477e 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 0ae30973..dab45eac 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) self.local_check(tx) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py index 7aee5219..6528b472 100755 --- a/compiler/tests/04_pinv_dec_1x_test.py +++ b/compiler/tests/04_pinv_dec_1x_test.py @@ -1,41 +1,42 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class pinv_dec_1x_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Checking 1x size decoder inverter") tx = factory.create(module_type="pinv_dec", size=1) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 4f227181..4a311beb 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pinvbuf_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 053e343c..b55fb74d 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pnand2_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) @@ -30,12 +31,12 @@ class pnand2_test(openram_test): # # Only DRC because well contacts will fail LVS # self.local_drc_check(tx) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index a934f698..04687ed8 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pnand3_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) @@ -30,12 +31,12 @@ class pnand3_test(openram_test): # # Only DRC because well contacts will fail LVS # self.local_drc_check(tx) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pnand4_test.py b/compiler/tests/04_pnand4_test.py index bceff7f9..52dea33d 100755 --- a/compiler/tests/04_pnand4_test.py +++ b/compiler/tests/04_pnand4_test.py @@ -1,37 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class pnand4_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 4-input nand gate") tx = factory.create(module_type="pnand4", size=1) self.local_check(tx) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index a68a7190..d9763025 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class pnor2_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py index 026deaee..9b7465f8 100755 --- a/compiler/tests/04_precharge_1rw_1r_test.py +++ b/compiler/tests/04_precharge_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class precharge_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check precharge array in multi-port OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Checking precharge for 1rw1r port 0") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") @@ -37,11 +37,12 @@ class precharge_test(openram_test): tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py index ae9740fb..eb14d032 100755 --- a/compiler/tests/04_precharge_pbitcell_test.py +++ b/compiler/tests/04_precharge_pbitcell_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class precharge_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check precharge in multi-port OPTS.bitcell = "pbitcell" @@ -42,11 +43,12 @@ class precharge_pbitcell_test(openram_test): tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 3d1d3832..da5e986a 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -1,37 +1,38 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class precharge_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") tx = factory.create(module_type="precharge", size=1) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pwrite_driver_test.py b/compiler/tests/04_pwrite_driver_test.py index 7d2d525b..a64b1817 100755 --- a/compiler/tests/04_pwrite_driver_test.py +++ b/compiler/tests/04_pwrite_driver_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import header, openram_test -import sys -import os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + @unittest.skip("SKIPPING 04_pwrite_driver_test") class pwrite_driver_test(openram_test): def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) + openram.init_openram("config_{0}".format(OPTS.tech_name), is_unit_test=True) debug.info(2, "Checking 1x pwrite_driver") tx = factory.create(module_type="pwrite_driver", size=1) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main() diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 5b4e7271..b702927a 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class replica_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import replica_pbitcell + openram.init_openram(config_file, is_unit_test=True) + from openram.modules import replica_pbitcell OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 @@ -41,11 +42,12 @@ class replica_pbitcell_test(openram_test): tx = replica_pbitcell(name="rpbc") self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py index c71e3190..36bc7e1e 100755 --- a/compiler/tests/04_wordline_driver_test.py +++ b/compiler/tests/04_wordline_driver_test.py @@ -1,38 +1,39 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + #@unittest.skip("SKIPPING 04_driver_test") - class wordline_driver_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check wordline driver for single port debug.info(2, "Checking driver") tx = factory.create(module_type="wordline_driver", cols=8) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/05_bitcell_array_1rw_1r_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py index 3ae9a7d7..982d0e7a 100755 --- a/compiler/tests/05_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py @@ -1,41 +1,42 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 2x2 array for cell_2port") a = factory.create(module_type="bitcell_array", cols=2, rows=2) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 738a038e..b6781e70 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -1,26 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing 8x8 array for 6t_cell") @@ -34,11 +34,12 @@ class array_test(openram_test): a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index 41eb7b0b..233b28c9 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -1,23 +1,24 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class dummy_row_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing dummy row for 6t_cell") a = factory.create(module_type="dummy_array", rows=1, cols=4) @@ -27,11 +28,12 @@ class dummy_row_test(openram_test): a = factory.create(module_type="dummy_array", rows=4, cols=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 8a05dcec..a0239263 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + #@unittest.skip("SKIPPING 05_pbitcell_array_test") class pbitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" @@ -46,11 +47,12 @@ class pbitcell_array_test(openram_test): a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_column_decoder_16row_test.py b/compiler/tests/06_column_decoder_16row_test.py index d34d6879..ca321f90 100755 --- a/compiler/tests/06_column_decoder_16row_test.py +++ b/compiler/tests/06_column_decoder_16row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 16 row sample for column_decoder") a = factory.create(module_type="column_decoder", col_addr_size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py index 26aeb899..9f001a20 100755 --- a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two debug.info(1, "Testing 132 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=132) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_132row_test.py b/compiler/tests/06_hierarchical_decoder_132row_test.py index d1655a25..6a2728ca 100755 --- a/compiler/tests/06_hierarchical_decoder_132row_test.py +++ b/compiler/tests/06_hierarchical_decoder_132row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two debug.info(1, "Testing 132 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=132) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py index aad79dd4..c809c8c6 100755 --- a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_16row_test.py b/compiler/tests/06_hierarchical_decoder_16row_test.py index fc379cc4..1ab4c081 100755 --- a/compiler/tests/06_hierarchical_decoder_16row_test.py +++ b/compiler/tests/06_hierarchical_decoder_16row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py index d81f6774..88c7d511 100755 --- a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder with non-power-of-two debug.info(1, "Testing 17 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=17) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_17row_test.py b/compiler/tests/06_hierarchical_decoder_17row_test.py index ff7d1662..80e2e0c7 100755 --- a/compiler/tests/06_hierarchical_decoder_17row_test.py +++ b/compiler/tests/06_hierarchical_decoder_17row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder with non-power-of-two debug.info(1, "Testing 17 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=17) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py index 7ec03133..7aaa644a 100755 --- a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 with 3x8 and 2-input NAND decoder debug.info(1, "Testing 32 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=32) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_32row_test.py b/compiler/tests/06_hierarchical_decoder_32row_test.py index 895b63dc..43c8d28d 100755 --- a/compiler/tests/06_hierarchical_decoder_32row_test.py +++ b/compiler/tests/06_hierarchical_decoder_32row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 with 3x8 and 2-input NAND decoder debug.info(1, "Testing 32 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=32) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py index c0058da4..abe8fb06 100755 --- a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 4096 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=4096) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_4096row_test.py b/compiler/tests/06_hierarchical_decoder_4096row_test.py index 14e3f113..49a7df0c 100755 --- a/compiler/tests/06_hierarchical_decoder_4096row_test.py +++ b/compiler/tests/06_hierarchical_decoder_4096row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 2x4 and 2-input NAND decoder debug.info(1, "Testing 4096 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=4096) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py index 5982e930..7f0f2006 100755 --- a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 3 x 3x8 and 3-input NAND decoder debug.info(1, "Testing 512 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=512) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_512row_test.py b/compiler/tests/06_hierarchical_decoder_512row_test.py index 6ad92d86..7dea9a13 100755 --- a/compiler/tests/06_hierarchical_decoder_512row_test.py +++ b/compiler/tests/06_hierarchical_decoder_512row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 3 x 3x8 and 3-input NAND decoder debug.info(1, "Testing 512 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=512) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py index 6dd3b4de..17b74447 100755 --- a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 3 x 2x4 and 3-input NAND decoder debug.info(1, "Testing 64 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=64) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_64row_test.py b/compiler/tests/06_hierarchical_decoder_64row_test.py index 37b97732..85a33cf2 100755 --- a/compiler/tests/06_hierarchical_decoder_64row_test.py +++ b/compiler/tests/06_hierarchical_decoder_64row_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # Checks 3 x 2x4 and 3-input NAND decoder debug.info(1, "Testing 64 row sample for hierarchical_decoder") a = factory.create(module_type="hierarchical_decoder", num_outputs=64) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index 2548e498..52c68e41 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -1,31 +1,31 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_decoder_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check hierarchical decoder for multi-port OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") @@ -64,11 +64,12 @@ class hierarchical_decoder_pbitcell_test(openram_test): a = factory.create(module_type="hierarchical_decoder", num_outputs=512) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py index 0cff264a..28e090be 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py @@ -1,41 +1,42 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode2x4_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for hierarchy_predecode2x4") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py index bb9523a9..b947a209 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode2x4_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # checking hierarchical precode 2x4 for multi-port OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index d8680f53..1677c565 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode2x4_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for hierarchy_predecode2x4") a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py index d6580991..6b70aed3 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode3x8_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # Use the 2 port cell since it is usually bigger/easier OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for hierarchy_predecode3x8") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py index 1ddc91df..44bea14b 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode3x8_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # checking hierarchical precode 3x8 for multi-port OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index 3ff4a252..aaa28cfd 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode3x8_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for hierarchy_predecode3x8") a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/06_hierarchical_predecode4x16_test.py b/compiler/tests/06_hierarchical_predecode4x16_test.py index ff855601..d4a98bf4 100755 --- a/compiler/tests/06_hierarchical_predecode4x16_test.py +++ b/compiler/tests/06_hierarchical_predecode4x16_test.py @@ -1,42 +1,43 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class hierarchical_predecode4x16_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # Use the 2 port cell since it is usually bigger/easier OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for hierarchy_predecode4x16") a = factory.create(module_type="hierarchical_predecode4x16") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py index 36d086a8..b997b493 100755 --- a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for 16-way column_mux_array port 0") a = factory.create(module_type="column_mux_array", columns=32, word_size=2, bitcell_bl="bl0", bitcell_br="br0") @@ -34,12 +34,12 @@ class column_mux_test(openram_test): a = factory.create(module_type="column_mux_array", columns=32, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_16mux_test.py b/compiler/tests/07_column_mux_array_16mux_test.py index 51634eae..f5356147 100755 --- a/compiler/tests/07_column_mux_array_16mux_test.py +++ b/compiler/tests/07_column_mux_array_16mux_test.py @@ -1,36 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for 16-way column_mux_array") a = factory.create(module_type="column_mux_array", columns=64, word_size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py index f217720e..b7ef7d83 100755 --- a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for 2-way column_mux_array port 0") a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0") @@ -34,12 +34,12 @@ class column_mux_test(openram_test): a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_2mux_test.py b/compiler/tests/07_column_mux_array_2mux_test.py index ba5145a4..dbaeb97d 100755 --- a/compiler/tests/07_column_mux_array_2mux_test.py +++ b/compiler/tests/07_column_mux_array_2mux_test.py @@ -1,36 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for 2-way column_mux_array") a = factory.create(module_type="column_mux_array", columns=16, word_size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py index 8f4fc364..4a63b806 100755 --- a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for 4-way column_mux_array port 0") a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") @@ -34,12 +34,12 @@ class column_mux_test(openram_test): a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_4mux_test.py b/compiler/tests/07_column_mux_array_4mux_test.py index 0d637ef6..34d452b0 100755 --- a/compiler/tests/07_column_mux_array_4mux_test.py +++ b/compiler/tests/07_column_mux_array_4mux_test.py @@ -1,36 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for 4-way column_mux_array") a = factory.create(module_type="column_mux_array", columns=16, word_size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py index 7d2f248e..29f5799e 100755 --- a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Testing sample for 8-way column_mux_array port 0") a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0") @@ -34,12 +34,12 @@ class column_mux_test(openram_test): a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_8mux_test.py b/compiler/tests/07_column_mux_array_8mux_test.py index 468d6507..a76daba4 100755 --- a/compiler/tests/07_column_mux_array_8mux_test.py +++ b/compiler/tests/07_column_mux_array_8mux_test.py @@ -1,36 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for 8-way column_mux_array") a = factory.create(module_type="column_mux_array", columns=32, word_size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/07_column_mux_array_pbitcell_test.py b/compiler/tests/07_column_mux_array_pbitcell_test.py index bceba919..450dd057 100755 --- a/compiler/tests/07_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_column_mux_array_pbitcell_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from testutils import * import sys, os +from testutils import * -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import OPTS +from openram.sram_factory import factory +from openram import debug class column_mux_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check single level column mux array in multi-port OPTS.bitcell = "pbitcell" @@ -44,12 +44,12 @@ class column_mux_pbitcell_test(openram_test): a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index 1cb4d12c..109c4b51 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class precharge_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check precharge array in multi-port OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() factory.reset() debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)") @@ -37,11 +37,12 @@ class precharge_1rw_1r_test(openram_test): pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1) self.local_check(pc) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 39d87476..8ff03813 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class precharge_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Checking 3 column precharge") pc = factory.create(module_type="precharge_array", columns=3) self.local_check(pc) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_buffer_array_test.py b/compiler/tests/08_wordline_buffer_array_test.py index 6ae422c4..6c8bcb89 100755 --- a/compiler/tests/08_wordline_buffer_array_test.py +++ b/compiler/tests/08_wordline_buffer_array_test.py @@ -1,37 +1,38 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class wordline_buffer_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check wordline driver for single port debug.info(2, "Checking driver") tx = factory.create(module_type="wordline_buffer_array", rows=8, cols=32) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py index cbfa1825..51251b15 100755 --- a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py +++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py @@ -1,43 +1,44 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class wordline_driver_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # Use the 2 port cell since it is usually bigger/easier OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # check wordline driver for single port debug.info(2, "Checking driver") tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_driver_array_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py index f3398346..adc9e043 100755 --- a/compiler/tests/08_wordline_driver_array_pbitcell_test.py +++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py @@ -1,26 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class wordline_driver_array_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check wordline driver for multi-port OPTS.bitcell = "pbitcell" @@ -33,11 +33,12 @@ class wordline_driver_array_pbitcell_test(openram_test): tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/08_wordline_driver_array_test.py b/compiler/tests/08_wordline_driver_array_test.py index ea982005..23d0721f 100755 --- a/compiler/tests/08_wordline_driver_array_test.py +++ b/compiler/tests/08_wordline_driver_array_test.py @@ -1,37 +1,38 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class wordline_driver_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check wordline driver for single port debug.info(2, "Checking driver") tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32) self.local_check(tx) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py index 8273a0ad..5e8d7b04 100755 --- a/compiler/tests/09_sense_amp_array_1rw_1r_test.py +++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py @@ -1,31 +1,31 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sense_amp_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1) @@ -39,11 +39,12 @@ class sense_amp_test(openram_test): a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/09_sense_amp_array_pbitcell_test.py b/compiler/tests/09_sense_amp_array_pbitcell_test.py index 4dfd966d..9996591a 100755 --- a/compiler/tests/09_sense_amp_array_pbitcell_test.py +++ b/compiler/tests/09_sense_amp_array_pbitcell_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys,os import unittest from testutils import * -import sys,os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class sense_amp_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) #check sense amp array for multi-port OPTS.bitcell = "pbitcell" @@ -36,11 +37,12 @@ class sense_amp_pbitcell_test(openram_test): a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py index 57429d2b..44aca204 100755 --- a/compiler/tests/09_sense_amp_array_spare_cols_test.py +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class sense_amp_array_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3") @@ -45,11 +46,12 @@ class sense_amp_array_spare_cols_test(openram_test): a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index aa21f181..9ef33a9a 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class sense_amp_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1) @@ -33,11 +34,12 @@ class sense_amp_test(openram_test): a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py index 534d5904..7c828947 100755 --- a/compiler/tests/10_write_driver_array_1rw_1r_test.py +++ b/compiler/tests/10_write_driver_array_1rw_1r_test.py @@ -1,31 +1,31 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_driver_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing write_driver_array for columns=8, word_size=8") a = factory.create(module_type="write_driver_array", columns=8, word_size=8) @@ -35,11 +35,12 @@ class write_driver_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py index cd5601ce..76299bed 100755 --- a/compiler/tests/10_write_driver_array_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_pbitcell_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class write_driver_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for multi-port OPTS.bitcell = "pbitcell" @@ -36,11 +37,12 @@ class write_driver_pbitcell_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py index bacfbdd9..fd6181c4 100755 --- a/compiler/tests/10_write_driver_array_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class write_driver_array_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3") @@ -45,11 +46,12 @@ class write_driver_array_spare_cols_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index fc17301e..15e1658e 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class write_driver_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") @@ -30,11 +31,12 @@ class write_driver_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py index 02c76300..bc6e914b 100755 --- a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py @@ -1,27 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os - -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_driver_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for multi-port OPTS.bitcell = "pbitcell" @@ -38,12 +37,12 @@ class write_driver_pbitcell_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py index e609ba43..35967ab5 100755 --- a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py @@ -1,27 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os - -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_driver_array_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") @@ -36,12 +35,12 @@ class write_driver_array_wmask_spare_cols_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4, num_spare_cols=3) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index 7c1fd7bc..7ed06287 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -1,27 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os - -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_driver_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") @@ -36,12 +35,12 @@ class write_driver_test(openram_test): a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py index 806381b5..5b695100 100755 --- a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py +++ b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py @@ -1,31 +1,31 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_mask_and_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) @@ -39,12 +39,12 @@ class write_mask_and_array_test(openram_test): a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py index fe43d0f2..7ba5f0bd 100755 --- a/compiler/tests/10_write_mask_and_array_pbitcell_test.py +++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py @@ -1,27 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os - -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_mask_and_array_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for multi-port OPTS.bitcell = "pbitcell" @@ -38,12 +37,12 @@ class write_mask_and_array_pbitcell_test(openram_test): a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 8a667145..bfcf8cfa 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -1,27 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os - -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class write_mask_and_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check write driver array for single port debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") @@ -36,12 +35,12 @@ class write_mask_and_array_test(openram_test): a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index 7d4779eb..20e28a00 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class dff_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) @@ -33,11 +34,12 @@ class dff_array_test(openram_test): a = factory.create(module_type="dff_array", rows=3, columns=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index e46a5f91..22328559 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class dff_buf_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) @@ -33,11 +34,12 @@ class dff_buf_array_test(openram_test): a = factory.create(module_type="dff_buf_array", rows=3, columns=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 354e5188..9bf05506 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 12_tri_gate_array_test") @@ -21,7 +21,7 @@ class tri_gate_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) @@ -31,11 +31,12 @@ class tri_gate_array_test(openram_test): a = factory.create(module_type="tri_gate_array", columns=16, word_size=8) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index b07dde74..717defbc 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class delay_chain_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py index 0f905d75..578d2072 100755 --- a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class replica_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 array left and right replica for dp cell") a = factory.create(module_type="replica_bitcell_array", @@ -34,11 +34,12 @@ class replica_bitcell_array_1rw_1r_test(openram_test): right_rbl=[1]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py index a07318f0..a509c7f0 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class replica_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 left replica array for dp cell") a = factory.create(module_type="replica_bitcell_array", @@ -33,11 +33,11 @@ class replica_bitcell_array_1rw_1r_test(openram_test): left_rbl=[0]) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py index 920a3d3e..a231f8ef 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class replica_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 non-replica array for dp cell") a = factory.create(module_type="replica_bitcell_array", @@ -32,11 +32,12 @@ class replica_bitcell_array_1rw_1r_test(openram_test): rbl=[1, 1]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index fc938bfb..6b4493b0 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -1,23 +1,24 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class replica_bitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 @@ -28,11 +29,12 @@ class replica_bitcell_array_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py index e5356d62..0ad40bad 100755 --- a/compiler/tests/14_replica_column_1rw_1r_test.py +++ b/compiler/tests/14_replica_column_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class replica_column_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing one left replica column for dual port") a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=0) @@ -41,11 +41,12 @@ class replica_column_test(openram_test): a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=5) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 07eeb16c..dd0ba841 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -1,24 +1,24 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class replica_column_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -34,11 +34,12 @@ class replica_column_test(openram_test): column_offset=num_spare_cols) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py index d72289a7..6e7e3f62 100755 --- a/compiler/tests/14_replica_pbitcell_array_test.py +++ b/compiler/tests/14_replica_pbitcell_array_test.py @@ -1,23 +1,24 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class replica_pbitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" @@ -42,11 +43,12 @@ class replica_pbitcell_array_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py index d7701539..cc8a0fa5 100755 --- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py @@ -1,18 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS # @unittest.skip("SKIPPING 05_global_bitcell_array_test") @@ -20,12 +21,12 @@ class global_bitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 2 x 4x4 global bitcell array for cell_1rw_1r") a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) @@ -35,12 +36,12 @@ class global_bitcell_array_test(openram_test): # a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0]) # self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_test.py index 7f4b8154..93a5c240 100755 --- a/compiler/tests/15_global_bitcell_array_test.py +++ b/compiler/tests/15_global_bitcell_array_test.py @@ -1,18 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from sram_factory import factory -import debug +import openram +from openram.sram_factory import factory +from openram import debug +from openram import OPTS # @unittest.skip("SKIPPING 05_global_bitcell_array_test") @@ -20,7 +21,7 @@ class global_bitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell") # a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) @@ -30,12 +31,12 @@ class global_bitcell_array_test(openram_test): a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index 0826586c..f759ffd8 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -1,18 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS # @unittest.skip("SKIPPING 05_local_bitcell_array_test") @@ -20,12 +21,12 @@ class local_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) @@ -43,12 +44,12 @@ class local_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py index 30c9c8e9..aaa38503 100755 --- a/compiler/tests/15_local_bitcell_array_test.py +++ b/compiler/tests/15_local_bitcell_array_test.py @@ -1,18 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS # @unittest.skip("SKIPPING 05_local_bitcell_array_test") @@ -20,7 +21,7 @@ class local_bitcell_array_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0]) @@ -30,12 +31,12 @@ class local_bitcell_array_test(openram_test): a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index ae6ce538..a20dd394 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -1,29 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -#Copyright (c) 2016-2021 Regents of the University of California and The Board -#of Regents for the Oklahoma Agricultural and Mechanical College -#(acting for and on behalf of Oklahoma State University) -#All rights reserved. +# Copyright (c) 2016-2022 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. # """ Run a regression test on a control_logic """ +import sys, os import unittest from testutils import header,openram_test -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check control logic for multi-port OPTS.bitcell = "pbitcell" @@ -48,11 +49,12 @@ class control_logic_test(openram_test): a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main() diff --git a/compiler/tests/16_control_logic_r_test.py b/compiler/tests/16_control_logic_r_test.py index 67fa2635..8cc507ca 100755 --- a/compiler/tests/16_control_logic_r_test.py +++ b/compiler/tests/16_control_logic_r_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for control_logic_r") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_rw_test.py b/compiler/tests/16_control_logic_rw_test.py index dd83f623..81ad0e2c 100755 --- a/compiler/tests/16_control_logic_rw_test.py +++ b/compiler/tests/16_control_logic_rw_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for control_logic_rw") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_w_test.py b/compiler/tests/16_control_logic_w_test.py index 4a828fdf..6777144c 100755 --- a/compiler/tests/16_control_logic_w_test.py +++ b/compiler/tests/16_control_logic_w_test.py @@ -1,35 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for control_logic_w") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w") self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_address_16rows_1rw_1r_test.py b/compiler/tests/18_port_address_16rows_1rw_1r_test.py index ffca57d3..28363c42 100755 --- a/compiler/tests/18_port_address_16rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_16rows_1rw_1r_test.py @@ -1,40 +1,41 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_address_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # Use the 2 port cell since it is usually bigger/easier OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_address_16rows_test.py b/compiler/tests/18_port_address_16rows_test.py index 36093297..aa708b24 100755 --- a/compiler/tests/18_port_address_16rows_test.py +++ b/compiler/tests/18_port_address_16rows_test.py @@ -1,34 +1,35 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_address_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_address_256rows_1rw_1r_test.py b/compiler/tests/18_port_address_256rows_1rw_1r_test.py index 8fef71fc..b8a23b63 100755 --- a/compiler/tests/18_port_address_256rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_256rows_1rw_1r_test.py @@ -1,40 +1,41 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_address_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # Use the 2 port cell since it is usually bigger/easier OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(1, "Port address 256 rows") a = factory.create("port_address", cols=256, rows=256, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_address_512rows_test.py b/compiler/tests/18_port_address_512rows_test.py index 03f8c455..5c0ee244 100755 --- a/compiler/tests/18_port_address_512rows_test.py +++ b/compiler/tests/18_port_address_512rows_test.py @@ -1,34 +1,35 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_address_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Port address 512 rows") a = factory.create("port_address", cols=256, rows=512, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py index 15ff8eee..1ba5ccc0 100755 --- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -40,11 +40,12 @@ class port_data_1rw_1r_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py index 3415711b..abf5cd5f 100755 --- a/compiler/tests/18_port_data_16mux_test.py +++ b/compiler/tests/18_port_data_16mux_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # import unittest from testutils import * import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -42,11 +42,12 @@ class port_data_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py index d907b50c..d7479126 100755 --- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -39,11 +39,12 @@ class port_data_1rw_1r_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py index 4b72d046..d9379f9d 100755 --- a/compiler/tests/18_port_data_2mux_test.py +++ b/compiler/tests/18_port_data_2mux_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -41,11 +41,12 @@ class port_data_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py index c5d163cf..bcb938bf 100755 --- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -39,11 +39,12 @@ class port_data_1rw_1r_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py index 84136361..aa8cec14 100755 --- a/compiler/tests/18_port_data_4mux_test.py +++ b/compiler/tests/18_port_data_4mux_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -41,11 +41,12 @@ class port_data_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py index 17c98ace..b45e9280 100755 --- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -40,11 +40,12 @@ class port_data_1rw_1r_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py index 781954cc..3e3d25cc 100755 --- a/compiler/tests/18_port_data_8mux_test.py +++ b/compiler/tests/18_port_data_8mux_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -42,11 +42,12 @@ class port_data_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py index 1c1197ee..a1a4240b 100755 --- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -38,11 +38,12 @@ class port_data_1rw_1r_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py index 7d775cd5..2ff0d453 100755 --- a/compiler/tests/18_port_data_nomux_test.py +++ b/compiler/tests/18_port_data_nomux_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -40,11 +40,12 @@ class port_data_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index e26be6e8..efbc00b4 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -1,25 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=8, num_words=16, @@ -62,7 +62,7 @@ class port_data_spare_cols_test(openram_test): OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c.num_words=16 c.words_per_row=1 @@ -105,11 +105,12 @@ class port_data_spare_cols_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index 5f58f670..6f256f32 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_wmask_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=16, write_size=4, @@ -64,7 +64,7 @@ class port_data_wmask_1rw_1r_test(openram_test): OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c.num_words = 16 c.words_per_row = 1 @@ -107,12 +107,12 @@ class port_data_wmask_1rw_1r_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index 406b6822..d243d03f 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -1,26 +1,25 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os - -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class port_data_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -69,7 +68,7 @@ class port_data_wmask_test(openram_test): OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c.num_words = 16 c.words_per_row = 1 @@ -112,12 +111,12 @@ class port_data_wmask_test(openram_test): a = factory.create("port_data", sram_config=c, port=1) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index e73a97fc..7982968e 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -1,27 +1,28 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + @unittest.skip("SKIPPING 19_multi_bank_test") class multi_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=4, num_words=16) @@ -59,11 +60,12 @@ class multi_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index be2ba0c0..94f67aaf 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -1,27 +1,28 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + @unittest.skip("SKIPPING 19_pmulti_bank_test") class multi_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent) @@ -64,11 +65,12 @@ class multi_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 539ebbc0..74638380 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psingle_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" @@ -30,7 +30,7 @@ class psingle_bank_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -67,11 +67,12 @@ class psingle_bank_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py index adc5d33e..1da7a246 100755 --- a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=2, num_words=128) @@ -38,11 +38,12 @@ class single_bank_1rw_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_16mux_test.py b/compiler/tests/19_single_bank_16mux_test.py index 8dd02db3..e6033ff6 100755 --- a/compiler/tests/19_single_bank_16mux_test.py +++ b/compiler/tests/19_single_bank_16mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -44,11 +44,12 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 31b8349b..e1cde699 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -63,11 +63,12 @@ class single_bank_1w_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py index dbed3cc6..a67d3ad1 100755 --- a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -39,11 +39,12 @@ class single_bank_1rw_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_2mux_test.py b/compiler/tests/19_single_bank_2mux_test.py index f5efc231..563b76fe 100755 --- a/compiler/tests/19_single_bank_2mux_test.py +++ b/compiler/tests/19_single_bank_2mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=4, num_words=16) @@ -34,11 +34,12 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py index 13387ac9..718ed148 100755 --- a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -39,11 +39,12 @@ class single_bank_1rw_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_4mux_test.py b/compiler/tests/19_single_bank_4mux_test.py index 7a58b401..54edd6f1 100755 --- a/compiler/tests/19_single_bank_4mux_test.py +++ b/compiler/tests/19_single_bank_4mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=4, num_words=16) @@ -34,11 +34,12 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py index f03aadc6..0d063dfb 100755 --- a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -40,11 +40,12 @@ class single_bank_1rw_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_8mux_test.py b/compiler/tests/19_single_bank_8mux_test.py index 56a3c549..3c5cf73d 100755 --- a/compiler/tests/19_single_bank_8mux_test.py +++ b/compiler/tests/19_single_bank_8mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -44,11 +44,12 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_global_bitline_test.py b/compiler/tests/19_single_bank_global_bitline_test.py index ead8decb..7b0ec4ba 100755 --- a/compiler/tests/19_single_bank_global_bitline_test.py +++ b/compiler/tests/19_single_bank_global_bitline_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() OPTS.local_array_size = 2 c = sram_config(word_size=4, @@ -64,11 +64,12 @@ class single_bank_1rw_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py index afb1129b..b0c9848b 100755 --- a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16) @@ -38,11 +38,12 @@ class single_bank_1rw_1r_test(openram_test): a = factory.create(module_type="bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_nomux_test.py b/compiler/tests/19_single_bank_nomux_test.py index 6ae084ec..795c04d4 100755 --- a/compiler/tests/19_single_bank_nomux_test.py +++ b/compiler/tests/19_single_bank_nomux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -42,11 +42,12 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index 97bcf5af..c779bc04 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class single_bank_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=4, num_words=16, @@ -58,11 +59,12 @@ class single_bank_spare_cols_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py index 77f7ba2e..9debdfb8 100755 --- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class single_bank_wmask_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=8, write_size=4, @@ -64,11 +64,12 @@ class single_bank_wmask_1rw_1r_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 08fe19f4..20f75924 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class single_bank_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config - + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=8, write_size=4, @@ -59,11 +59,12 @@ class single_bank_wmask_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 0c24ff3b..da9cfaec 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 1 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -47,11 +47,12 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index c8606bae..c917a63c 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 1 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=8, write_size=4, @@ -48,12 +48,12 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 51be2cab..f94167dd 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -45,11 +45,12 @@ class psram_1bank_2mux_1w_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 133c81d1..803d86a1 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_2mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -47,11 +47,12 @@ class psram_1bank_2mux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 0995e49f..5a272da8 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -1,33 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=64, @@ -47,11 +47,12 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py index 93736a53..aeede7d6 100755 --- a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=2, num_words=256, @@ -46,11 +46,12 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_16mux_test.py b/compiler/tests/20_sram_1bank_16mux_test.py index 6461c5a6..12e19c3b 100755 --- a/compiler/tests/20_sram_1bank_16mux_test.py +++ b/compiler/tests/20_sram_1bank_16mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_8mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -50,11 +50,12 @@ class sram_1bank_8mux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py index 08922ede..e554e770 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -48,11 +48,12 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index b5d9d776..8c94902e 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -46,11 +46,11 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py index abbb2347..75b5b4be 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -48,11 +48,12 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 5eabef8b..cebb57c8 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -46,11 +46,12 @@ class psram_1bank_2mux_1w_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py index fc4a32e8..1ae8ef5b 100755 --- a/compiler/tests/20_sram_1bank_2mux_global_test.py +++ b/compiler/tests/20_sram_1bank_2mux_global_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_global_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.local_array_size = 8 if OPTS.tech_name == "sky130": @@ -51,11 +51,12 @@ class sram_1bank_2mux_global_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 85041348..808329e9 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -50,11 +50,12 @@ class sram_1bank_2mux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py index d24fa62f..92e1993b 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -53,12 +53,12 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 84830d5c..51a4163d 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -52,12 +52,12 @@ class sram_1bank_2mux_wmask_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index 4df1bcca..f999ab2d 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING sram_1bank_32b_1024_wmask_test") @@ -21,8 +21,8 @@ class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -52,12 +52,12 @@ class sram_1bank_32b_1024_wmask_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py index 905bf1e4..672429b4 100755 --- a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=64, @@ -46,11 +46,12 @@ class sram_1bank_4mux_1rw_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 0fdf883a..ecde15bf 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_4mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -50,11 +50,12 @@ class sram_1bank_4mux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index bc1f824d..3fd26b2c 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=2, num_words=128, @@ -46,11 +46,12 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index a670744a..d5e66036 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_8mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -50,11 +50,12 @@ class sram_1bank_8mux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index 561074a1..108e5306 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16, @@ -48,11 +48,12 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index e8e18b7a..3c58404f 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -1,32 +1,32 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() c = sram_config(word_size=4, num_words=16, @@ -46,11 +46,12 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index 99131037..4991e640 100755 --- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -51,12 +51,12 @@ class sram_1bank_nomux_spare_cols_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 59e309df..81472fb2 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_nomux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -49,11 +50,12 @@ class sram_1bank_nomux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py index a7326df3..cbe2e805 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_sparecols_test, not working yet") @@ -21,8 +21,8 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -54,12 +54,12 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index 5eb10212..361874a8 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -1,27 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -52,12 +52,12 @@ class sram_1bank_nomux_wmask_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py index 5010a3de..9db0d9f4 100755 --- a/compiler/tests/20_sram_1bank_ring_test.py +++ b/compiler/tests/20_sram_1bank_ring_test.py @@ -1,28 +1,28 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_1bank_nomux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.supply_pin_type = "ring" - from modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -51,11 +51,12 @@ class sram_1bank_nomux_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index e2d144bf..650b0df7 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("Multibank is not working yet.") @@ -21,8 +21,8 @@ class sram_2bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config c = sram_config(word_size=16, num_words=32, num_banks=2) @@ -91,11 +91,12 @@ class sram_2bank_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index a5677a13..22a43f77 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -1,36 +1,37 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + @unittest.skip("SKIPPING 21_hspice_delay_test") class timing_sram_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import delay - from modules import sram_config + from openram.characterizer import delay + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -57,7 +58,7 @@ class timing_sram_test(openram_test): corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay(s.s, tempspice, corner) - import tech + from openram import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] load_slews = [] @@ -105,11 +106,12 @@ class timing_sram_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 0ebcb167..81b037ef 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS +import openram +from openram import OPTS @unittest.skip("SKIPPING 21_hspice_setuphold_test") @@ -19,17 +19,17 @@ class timing_setup_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import setup_hold - import tech + from openram.characterizer import setup_hold + from openram import tech slews = [tech.spice["rise_time"]*2] corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) @@ -58,11 +58,12 @@ class timing_setup_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 16924f0b..5a9d1213 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -1,19 +1,20 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + # @unittest.skip("SKIPPING 21_model_delay_test") class model_delay_test(openram_test): @@ -21,18 +22,18 @@ class model_delay_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import delay - from characterizer import elmore - from modules import sram - from modules import sram_config + from openram.characterizer import delay + from openram.characterizer import elmore + from openram import sram + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -61,7 +62,7 @@ class model_delay_test(openram_test): d = delay(s.s, tempspice, corner) m = elmore(s.s, tempspice, corner) - import tech + from openram import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] load_slews = [] @@ -100,11 +101,12 @@ class model_delay_test(openram_test): self.assertTrue(self.check_golden_data(spice_delays,model_delays,error_tolerance)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index 3935ac3d..249bea34 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -1,35 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class timing_sram_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import delay - from modules import sram_config + from openram.characterizer import delay + from openram import sram_config c = sram_config(word_size=1, num_words=16, num_banks=1, @@ -48,7 +49,7 @@ class timing_sram_test(openram_test): corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay(s.s, tempspice, corner) - import tech + from openram import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] load_slews = [] @@ -97,11 +98,12 @@ class timing_sram_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py index 94ed2aba..a144be64 100755 --- a/compiler/tests/21_ngspice_delay_global_test.py +++ b/compiler/tests/21_ngspice_delay_global_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 21_ngspice_delay_global_test") @@ -21,17 +21,17 @@ class timing_sram_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import delay - from modules import sram_config + from openram.characterizer import delay + from openram import sram_config OPTS.local_array_size = 2 if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -65,7 +65,7 @@ class timing_sram_test(openram_test): corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay(s.s, tempspice, corner) - import tech + from openram import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] load_slews = [] @@ -114,11 +114,12 @@ class timing_sram_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 28db8511..9c43e69b 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -1,35 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class timing_sram_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import delay - from modules import sram_config + from openram.characterizer import delay + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -56,7 +57,7 @@ class timing_sram_test(openram_test): corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay(s.s, tempspice, corner) - import tech + from openram import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] load_slews = [] @@ -105,11 +106,12 @@ class timing_sram_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 70adfaaa..7774aaf4 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -1,34 +1,34 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS +import openram +from openram import OPTS class timing_setup_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import setup_hold - import tech + from openram.characterizer import setup_hold + from openram import tech slews = [tech.spice["rise_time"]*2] corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) @@ -58,11 +58,12 @@ class timing_setup_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) reload(characterizer) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_regression_delay_test.py b/compiler/tests/21_regression_delay_test.py index 94ece131..99ce1ac4 100755 --- a/compiler/tests/21_regression_delay_test.py +++ b/compiler/tests/21_regression_delay_test.py @@ -1,19 +1,20 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + # @unittest.skip("SKIPPING 21_regression_model_test") class regression_model_test(openram_test): @@ -21,18 +22,18 @@ class regression_model_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import linear_regression - from characterizer import neural_network - from modules import sram - from modules import sram_config + from openram.characterizer import linear_regression + from openram.characterizer import neural_network + from openram import sram + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -66,11 +67,12 @@ class regression_model_test(openram_test): accuracy_requirement = 0.75 self.assertTrue(scores['rise_delay'] >= accuracy_requirement) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py index 705f432e..cd6125ab 100755 --- a/compiler/tests/21_xyce_delay_test.py +++ b/compiler/tests/21_xyce_delay_test.py @@ -1,36 +1,36 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class timing_sram_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="xyce" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import delay - from modules import sram_config + from openram.characterizer import delay + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -57,7 +57,7 @@ class timing_sram_test(openram_test): corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) d = delay(s.s, tempspice, corner) - import tech + from openram import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] load_slews = [] @@ -105,11 +105,12 @@ class timing_sram_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py index c2962c48..3d516770 100755 --- a/compiler/tests/21_xyce_setuphold_test.py +++ b/compiler/tests/21_xyce_setuphold_test.py @@ -1,34 +1,34 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS +import openram +from openram import OPTS class timing_setup_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.spice_name="Xyce" OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import setup_hold - import tech + from openram.characterizer import setup_hold + from openram import tech slews = [tech.spice["rise_time"]*2] corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) @@ -57,11 +57,12 @@ class timing_setup_test(openram_test): self.assertTrue(self.check_golden_data(data,golden_data,0.25)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index f1d3707f..790358fc 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -1,26 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_2mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -35,10 +35,10 @@ class psram_1bank_2mux_func_test(openram_test): # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) @@ -57,11 +57,12 @@ class psram_1bank_2mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 1e504625..50e2fd2a 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?") @@ -21,7 +21,7 @@ class psram_1bank_4mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -36,10 +36,10 @@ class psram_1bank_4mux_func_test(openram_test): # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=2, num_words=256, num_banks=1) @@ -59,11 +59,12 @@ class psram_1bank_4mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index c2587221..d0a01f24 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test") @@ -21,7 +21,7 @@ class psram_1bank_8mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -36,10 +36,10 @@ class psram_1bank_8mux_func_test(openram_test): # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=4, num_words=256, num_banks=1) @@ -58,11 +58,12 @@ class psram_1bank_8mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 95fcdb14..5334a405 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -1,26 +1,27 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + #@unittest.skip("SKIPPING 22_psram_1bank_nomux_func_test") class psram_1bank_nomux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -35,10 +36,10 @@ class psram_1bank_nomux_func_test(openram_test): # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) @@ -57,11 +58,12 @@ class psram_1bank_nomux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 3aafb76a..e68dab2a 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test") @@ -21,17 +21,17 @@ class sram_1bank_2mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -56,11 +56,12 @@ class sram_1bank_2mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py index 4b3b3927..d97627ca 100755 --- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test") @@ -21,17 +21,17 @@ class sram_1bank_2mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config OPTS.local_array_size = 8 if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -57,11 +57,12 @@ class sram_1bank_2mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py index 20570a6c..aa8bcfc2 100755 --- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test") @@ -21,17 +21,17 @@ class sram_1bank_2mux_sparecols_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -57,11 +57,12 @@ class sram_1bank_2mux_sparecols_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index f2bee002..7c65c2a9 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test") @@ -21,17 +21,17 @@ class sram_1bank_4mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -56,11 +56,12 @@ class sram_1bank_4mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index 61758281..bee23ef4 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test") @@ -21,20 +21,20 @@ class sram_1bank_8mux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional + from openram.characterizer import functional if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) - from modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -59,11 +59,12 @@ class sram_1bank_8mux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py index 76116485..99133104 100755 --- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py @@ -1,26 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class psram_1bank_nomux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -28,14 +28,14 @@ class psram_1bank_nomux_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) @@ -51,11 +51,12 @@ class psram_1bank_nomux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 5617b3fe..5ec95c36 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 22_sram_func_test") @@ -21,17 +21,17 @@ class sram_1bank_nomux_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -56,11 +56,12 @@ class sram_1bank_nomux_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py index 5b3e0908..765dd571 100755 --- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 22_sram_func_test") @@ -21,17 +21,17 @@ class sram_1bank_nomux_sparecols_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -56,11 +56,12 @@ class sram_1bank_nomux_sparecols_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py index 09b77170..f690437b 100755 --- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py @@ -1,26 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -28,14 +28,14 @@ class sram_wmask_1w_1r_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -63,12 +63,12 @@ class sram_wmask_1w_1r_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index 570b515e..565c69f8 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING sram_wmask_func_test") @@ -21,17 +21,17 @@ class sram_wmask_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 @@ -58,11 +58,12 @@ class sram_wmask_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/23_lib_sram_linear_regression_test.py b/compiler/tests/23_lib_sram_linear_regression_test.py index 642c3b51..79c021d6 100755 --- a/compiler/tests/23_lib_sram_linear_regression_test.py +++ b/compiler/tests/23_lib_sram_linear_regression_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + #@unittest.skip("SKIPPING 23_lib_sram_linear_regression_test") class lib_sram_linear_regression_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.nominal_corner_only = False OPTS.netlist_only = True OPTS.model_name = "linear_regression" @@ -31,9 +32,9 @@ class lib_sram_linear_regression_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from characterizer import lib - from modules import sram - from modules import sram_config + from openram.characterizer import lib + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, @@ -63,17 +64,12 @@ class lib_sram_linear_regression_test(openram_test): golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname) self.assertTrue(self.isapproxdiff(libname,golden,0.15)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) - - - - - - diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 7a46aec5..71d00a85 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + #@unittest.skip("SKIPPING 23_lib_sram_model_corners_test") class lib_model_corners_lib_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.nominal_corner_only = False OPTS.netlist_only = True @@ -30,9 +31,9 @@ class lib_model_corners_lib_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from characterizer import lib - from modules import sram - from modules import sram_config + from openram.characterizer import lib + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, @@ -72,17 +73,12 @@ class lib_model_corners_lib_test(openram_test): golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname) self.assertTrue(self.isapproxdiff(libname,golden,0.15)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) - - - - - - diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index ec918b00..183efc29 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -1,25 +1,26 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + #@unittest.skip("SKIPPING 23_lib_sram_model_test") class lib_sram_model_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.nominal_corner_only = False OPTS.netlist_only = True @@ -30,9 +31,9 @@ class lib_sram_model_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from characterizer import lib - from modules import sram - from modules import sram_config + from openram.characterizer import lib + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, @@ -62,17 +63,12 @@ class lib_sram_model_test(openram_test): golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname) self.assertTrue(self.isapproxdiff(libname,golden,0.15)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) - - - - - - diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index b509a1b9..b9f1ae19 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -1,34 +1,35 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + @unittest.skip("SKIPPING 23_lib_sram_prune_test") class lib_sram_prune_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import lib + from openram.characterizer import lib if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) @@ -39,8 +40,8 @@ class lib_sram_prune_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from modules import sram - from modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, @@ -72,17 +73,12 @@ class lib_sram_prune_test(openram_test): self.assertTrue(self.isapproxdiff(libname,golden,0.40)) reload(characterizer) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) - - - - - - diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 34397ada..961dc9e5 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -1,32 +1,33 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re import unittest from testutils import * -import sys, os,re -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + class lib_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import lib + from openram.characterizer import lib if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) @@ -37,8 +38,8 @@ class lib_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from modules import sram - from modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, @@ -69,17 +70,12 @@ class lib_test(openram_test): self.assertTrue(self.isapproxdiff(libname,golden,0.40)) reload(characterizer) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) - - - - - - diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 675daed8..3d38462f 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -1,18 +1,18 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS @unittest.skip("SKIPPING 24_lef_sram_test") @@ -20,11 +20,11 @@ class lef_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.route_supplies=False OPTS.check_lvsdrc=False - from modules import sram - from modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1) @@ -46,11 +46,12 @@ class lef_test(openram_test): golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), leffile) self.assertTrue(self.isdiff(lefname, golden)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/25_verilog_multibank_test.py b/compiler/tests/25_verilog_multibank_test.py index 91fb04ae..acd3bc12 100755 --- a/compiler/tests/25_verilog_multibank_test.py +++ b/compiler/tests/25_verilog_multibank_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) -import globals -from globals import OPTS -import debug + +import openram +from openram import debug +from openram import OPTS class multibank_verilog_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.route_supplies=False OPTS.check_lvsdrc=False OPTS.netlist_only=True - from modules import sram - from modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=2) @@ -50,12 +50,12 @@ class multibank_verilog_test(openram_test): one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bfile) self.assertTrue(self.isdiff(v1bname, one_golden)) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index be2528b6..4d6e4456 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -1,30 +1,30 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS class verilog_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.route_supplies=False OPTS.check_lvsdrc=False OPTS.netlist_only=True - from modules import sram - from modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1) @@ -44,11 +44,12 @@ class verilog_test(openram_test): golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile) self.assertTrue(self.isdiff(vname, golden)) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index 7dbd56a6..6d2f608c 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -1,20 +1,20 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # """ Run regression tests/pex test on an extracted pinv to ensure pex functionality with HSPICE. """ +import sys, os import unittest from testutils import header, openram_test -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS @unittest.skip("SKIPPING 26_hspice_pex_pinv_test") @@ -22,8 +22,8 @@ class hspice_pex_pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import pinv + openram.init_openram(config_file, is_unit_test=True) + from openram.modules import pinv # load the hspice OPTS.spice_name="hspice" @@ -31,7 +31,7 @@ class hspice_pex_pinv_test(openram_test): # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) # generate the pinv @@ -70,7 +70,7 @@ class hspice_pex_pinv_test(openram_test): # assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\ # .format(pex_delay,sp_delay) - globals.end_openram() + openram.end_openram() def simulate_delay(self, test_module, top_level_name): from charutils import parse_spice_list @@ -84,8 +84,8 @@ class hspice_pex_pinv_test(openram_test): def write_simulation(self, sim_file, cir_file, top_module_name): """ write pex spice simulation for a pinv test""" - import tech - from characterizer import measurements, stimuli + from openram import tech + from openram.characterizer import measurements, stimuli corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) sim_file = open(OPTS.openram_temp + sim_file, "w") simulation = stimuli(sim_file, corner) @@ -131,7 +131,7 @@ class hspice_pex_pinv_test(openram_test): # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main() diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index 31a6d5ae..09ee5914 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -1,27 +1,28 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # """ Run regression tests/pex test on an extracted pinv to ensure pex functionality with Ngspice. """ +import sys, os import unittest from testutils import header,openram_test -import sys, os -import globals -from globals import OPTS -import debug +import openram +from openram import debug +from openram import OPTS + @unittest.skip("SKIPPING 26_ngspice_pex_pinv_test") class ngspice_pex_pinv_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - import pinv + openram.init_openram(config_file, is_unit_test=True) + from openram.modules import pinv # load the ngspice OPTS.spice_name="ngspice" @@ -29,7 +30,7 @@ class ngspice_pex_pinv_test(openram_test): # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) # generate the pinv module @@ -68,7 +69,7 @@ class ngspice_pex_pinv_test(openram_test): # assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\ # .format(pex_delay,sp_delay) - globals.end_openram() + openram.end_openram() def simulate_delay(self, test_module, top_level_name): from charutils import parse_spice_list @@ -87,8 +88,8 @@ class ngspice_pex_pinv_test(openram_test): def write_simulation(self, sim_file, cir_file, top_module_name): """ write pex spice simulation for a pinv test""" - import tech - from characterizer import measurements, stimuli + from openram import tech + from openram.characterizer import measurements, stimuli corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) sim_file = open(sim_file, "w") simulation = stimuli(sim_file, corner) @@ -135,9 +136,10 @@ class ngspice_pex_pinv_test(openram_test): sim_file.close() return simulation + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main() diff --git a/compiler/tests/26_sram_pex_test.py b/compiler/tests/26_sram_pex_test.py index c8b101cb..fb6968fb 100755 --- a/compiler/tests/26_sram_pex_test.py +++ b/compiler/tests/26_sram_pex_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 26_sram_pex_test") @@ -21,16 +21,16 @@ class sram_pex_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.use_pex = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) @@ -49,11 +49,12 @@ class sram_pex_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/30_openram_back_end_library_test.py b/compiler/tests/30_openram_back_end_library_test.py new file mode 100755 index 00000000..155d4f1c --- /dev/null +++ b/compiler/tests/30_openram_back_end_library_test.py @@ -0,0 +1,99 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os, re +import shutil +import getpass +import unittest +from testutils import * + +import openram +from openram import debug +from openram import OPTS + + +class openram_back_end_library_test(openram_test): + + def runTest(self): + global OPTS + # Set output name and path before calling init_openram() + out_file = "testsram" + out_path = "/tmp/testsram_{0}_{1}_{2}/".format(OPTS.tech_name, getpass.getuser(), os.getpid()) + OPTS.output_name = out_file + OPTS.output_path = out_path + + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) + config_file = "{}/tests/configs/config_back_end".format(os.getenv("OPENRAM_HOME")) + # FIXME: is_unit_test=True causes error + openram.init_openram(config_file, is_unit_test=False) + + debug.info(1, "Testing top-level back-end sram_compiler.py with 2-bit, 16 word SRAM.") + + # make sure we start without the files existing + if os.path.exists(out_path): + shutil.rmtree(out_path, ignore_errors=True) + self.assertEqual(os.path.exists(out_path), False) + + try: + os.makedirs(out_path, 0o0750) + except OSError as e: + if e.errno == 17: # errno.EEXIST + os.chmod(out_path, 0o0750) + + # Update OPTS to match sram_compiler library test + OPTS.output_name = out_file + OPTS.output_path = out_path + OPTS.num_threads = 2 + + # Create an SRAM using the library + from openram import sram + s = sram() + s.save() + + # assert an error until we actually check a resul + for extension in ["gds", "v", "lef", "sp", "lvs.sp"]: + filename = "{0}{1}.{2}".format(out_path, out_file, extension) + debug.info(1, "Checking for file: " + filename) + self.assertEqual(os.path.exists(filename), True) + + # check if the auxiliary scripts were created + for script_name in ["run_drc.sh", "run_lvs.sh"]: + filename = "{0}{1}".format(out_path, script_name) + debug.info(1, "Checking for file: " + filename) + self.assertEqual(os.path.exists(filename), True) + + # Make sure there is any .lib file + import glob + files = glob.glob('{0}*.lib'.format(out_path)) + self.assertTrue(len(files)>0) + + # Make sure there is any .html file + if os.path.exists(out_path): + datasheets = glob.glob('{0}*html'.format(out_path)) + self.assertTrue(len(datasheets)>0) + + # grep any errors from the output + output_log = open("{0}{1}.log".format(out_path, out_file), "r") + output = output_log.read() + output_log.close() + self.assertEqual(len(re.findall('ERROR', output)), 0) + self.assertEqual(len(re.findall('WARNING', output)), 0) + + # now clean up the directory + if not OPTS.keep_temp: + if os.path.exists(out_path): + shutil.rmtree(out_path, ignore_errors=True) + self.assertEqual(os.path.exists(out_path), False) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 9d5b1e42..ab884d0c 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -1,19 +1,20 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re +import shutil +import getpass import unittest from testutils import * -import sys, os, re, shutil -import globals -from globals import OPTS -import debug -import getpass +import openram +from openram import debug +from openram import OPTS class openram_back_end_test(openram_test): @@ -21,9 +22,9 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) config_file = "{}/tests/configs/config_back_end".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) - debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") + debug.info(1, "Testing top-level back-end sram_compiler.py with 2-bit, 16 word SRAM.") out_file = "testsram" out_path = "/tmp/testsram_{0}_{1}_{2}/".format(OPTS.tech_name, getpass.getuser(), os.getpid()) @@ -54,16 +55,16 @@ class openram_back_end_test(openram_test): # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") - exe_name = "{0}/openram.py ".format(OPENRAM_HOME) + exe_name = "{0}/../sram_compiler.py ".format(OPENRAM_HOME) else: - exe_name = "{0}{1}/openram.py ".format(OPTS.coverage_exe, OPENRAM_HOME) + exe_name = "{0}{1}/../sram_compiler.py ".format(OPTS.coverage_exe, OPENRAM_HOME) config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME) - cmd = "{0} -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, - out_file, - out_path, - options, - config_name, - out_path) + cmd = "{0} -o {1} -p {2} {3} {4} > {5}/output.log".format(exe_name, + out_file, + out_path, + options, + config_name, + out_path) debug.info(1, cmd) os.system(cmd) @@ -102,11 +103,12 @@ class openram_back_end_test(openram_test): shutil.rmtree(out_path, ignore_errors=True) self.assertEqual(os.path.exists(out_path), False) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/30_openram_front_end_library_test.py b/compiler/tests/30_openram_front_end_library_test.py new file mode 100755 index 00000000..d6343c27 --- /dev/null +++ b/compiler/tests/30_openram_front_end_library_test.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os, re +import shutil +import getpass +import unittest +from testutils import * + +import openram +from openram import debug +from openram import OPTS + + +class openram_front_end_library_test(openram_test): + + def runTest(self): + global OPTS + # Set output name and path before calling init_openram() + out_file = "testsram" + out_path = "/tmp/testsram_{0}_{1}_{2}/".format(OPTS.tech_name, getpass.getuser(), os.getpid()) + OPTS.output_name = out_file + OPTS.output_path = out_path + + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) + config_file = "{}/tests/configs/config_front_end".format(os.getenv("OPENRAM_HOME")) + # FIXME: is_unit_test=True causes error + openram.init_openram(config_file, is_unit_test=False) + + debug.info(1, "Testing top-level front-end library with 2-bit, 16 word SRAM.") + + # make sure we start without the files existing + if os.path.exists(out_path): + shutil.rmtree(out_path, ignore_errors=True) + self.assertEqual(os.path.exists(out_path), False) + + try: + os.makedirs(out_path, 0o0750) + except OSError as e: + if e.errno == 17: # errno.EEXIST + os.chmod(out_path, 0o0750) + + # Update OPTS to match sram_compiler library test + OPTS.output_name = out_file + OPTS.output_path = out_path + OPTS.check_lvsdrc = False + OPTS.num_threads = 2 + + # Create an SRAM using the library + from openram import sram + s = sram() + s.save() + + # assert an error until we actually check a result + for extension in ["v", "lef", "sp", "gds"]: + filename = "{0}{1}.{2}".format(out_path, out_file, extension) + debug.info(1, "Checking for file: " + filename) + self.assertEqual(os.path.exists(filename), True) + + # Make sure there is any .lib file + import glob + files = glob.glob('{0}*.lib'.format(out_path)) + self.assertTrue(len(files)>0) + + # Make sure there is any .html file + if os.path.exists(out_path): + datasheets = glob.glob('{0}*html'.format(out_path)) + self.assertTrue(len(datasheets)>0) + + # grep any errors from the output + output_log = open("{0}{1}.log".format(out_path, out_file), "r") + output = output_log.read() + output_log.close() + self.assertEqual(len(re.findall('ERROR', output)), 0) + self.assertEqual(len(re.findall('WARNING', output)), 0) + + # now clean up the directory + if not OPTS.keep_temp: + if os.path.exists(out_path): + shutil.rmtree(out_path, ignore_errors=True) + self.assertEqual(os.path.exists(out_path), False) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 489ea26c..7f5fb76c 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -1,19 +1,20 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os, re +import shutil +import getpass import unittest from testutils import * -import sys, os, re, shutil -import globals -from globals import OPTS -import debug -import getpass +import openram +from openram import debug +from openram import OPTS class openram_front_end_test(openram_test): @@ -21,9 +22,9 @@ class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) config_file = "{}/tests/configs/config_front_end".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) - debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") + debug.info(1, "Testing top-level front-end sram_compiler.py with 2-bit, 16 word SRAM.") out_file = "testsram" out_path = "/tmp/testsram_{0}_{1}_{2}".format(OPTS.tech_name, getpass.getuser(), os.getpid()) @@ -54,16 +55,16 @@ class openram_front_end_test(openram_test): # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") - exe_name = "{0}/openram.py ".format(OPENRAM_HOME) + exe_name = "{0}/../sram_compiler.py ".format(OPENRAM_HOME) else: - exe_name = "{0}{1}/openram.py ".format(OPTS.coverage_exe, OPENRAM_HOME) + exe_name = "{0}{1}/../sram_compiler.py ".format(OPTS.coverage_exe, OPENRAM_HOME) config_name = "{0}/tests/configs/config_front_end.py".format(OPENRAM_HOME) - cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, - out_file, - out_path, - options, - config_name, - out_path) + cmd = "{0} -n -o {1} -p {2} {3} {4} > {5}/output.log".format(exe_name, + out_file, + out_path, + options, + config_name, + out_path) debug.info(1, cmd) os.system(cmd) @@ -96,11 +97,12 @@ class openram_front_end_test(openram_test): shutil.rmtree(out_path, ignore_errors=True) self.assertEqual(os.path.exists(out_path), False) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1k_1rw1r_func_test.py b/compiler/tests/50_riscv_1k_1rw1r_func_test.py index 2b770111..ce82b02c 100755 --- a/compiler/tests/50_riscv_1k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_1k_1rw1r_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=256, @@ -54,11 +54,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1k_1rw_func_test.py b/compiler/tests/50_riscv_1k_1rw_func_test.py index 9623f4af..5cd1ae6c 100755 --- a/compiler/tests/50_riscv_1k_1rw_func_test.py +++ b/compiler/tests/50_riscv_1k_1rw_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=256, @@ -56,11 +56,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1rw1r_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py index 4b864193..9fe291b8 100755 --- a/compiler/tests/50_riscv_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_1rw1r_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -29,14 +29,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=32, @@ -54,11 +54,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1rw1r_phys_test.py b/compiler/tests/50_riscv_1rw1r_phys_test.py index 47774828..f0e46162 100755 --- a/compiler/tests/50_riscv_1rw1r_phys_test.py +++ b/compiler/tests/50_riscv_1rw1r_phys_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS # @unittest.skip("SKIPPING 50_riscv_phys_test") @@ -21,14 +21,14 @@ class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 OPTS.local_array_size = 16 - globals.setup_bitcell() + openram.setup_bitcell() OPTS.route_supplies = False OPTS.perimeter_pins = False @@ -51,11 +51,12 @@ class riscv_phys_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py index ee157a44..5afe61af 100755 --- a/compiler/tests/50_riscv_1rw_func_test.py +++ b/compiler/tests/50_riscv_1rw_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -37,14 +37,14 @@ class riscv_func_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 OPTS.local_array_size = 16 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=64, @@ -64,11 +64,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py index c4e574c1..b53225fe 100755 --- a/compiler/tests/50_riscv_1rw_phys_test.py +++ b/compiler/tests/50_riscv_1rw_phys_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS #@unittest.skip("SKIPPING 50_riscv_phys_test") @@ -21,8 +21,8 @@ class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - from modules import sram_config + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 @@ -35,7 +35,7 @@ class riscv_phys_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 OPTS.local_array_size = 16 - globals.setup_bitcell() + openram.setup_bitcell() OPTS.route_supplies = False OPTS.perimeter_pins = False @@ -59,11 +59,12 @@ class riscv_phys_test(openram_test): a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_2k_1rw1r_func_test.py b/compiler/tests/50_riscv_2k_1rw1r_func_test.py index ffa7ca03..416fd17b 100755 --- a/compiler/tests/50_riscv_2k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_2k_1rw1r_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=512, @@ -54,11 +54,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_2k_1rw_func_test.py b/compiler/tests/50_riscv_2k_1rw_func_test.py index a48a03c0..ff26deb7 100755 --- a/compiler/tests/50_riscv_2k_1rw_func_test.py +++ b/compiler/tests/50_riscv_2k_1rw_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=512, @@ -56,11 +56,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_4k_1rw1r_func_test.py b/compiler/tests/50_riscv_4k_1rw1r_func_test.py index 431b5390..85af4f92 100755 --- a/compiler/tests/50_riscv_4k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_4k_1rw1r_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=1024, @@ -54,11 +54,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_4k_1rw_func_test.py b/compiler/tests/50_riscv_4k_1rw_func_test.py index 45254ac4..04b8e985 100755 --- a/compiler/tests/50_riscv_4k_1rw_func_test.py +++ b/compiler/tests/50_riscv_4k_1rw_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=1024, @@ -56,11 +56,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_512b_1rw1r_func_test.py b/compiler/tests/50_riscv_512b_1rw1r_func_test.py index 26682139..60cc741c 100755 --- a/compiler/tests/50_riscv_512b_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_512b_1rw1r_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=128, @@ -54,11 +54,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_512b_1rw_func_test.py b/compiler/tests/50_riscv_512b_1rw_func_test.py index 0af228a9..7faefad7 100755 --- a/compiler/tests/50_riscv_512b_1rw_func_test.py +++ b/compiler/tests/50_riscv_512b_1rw_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=128, @@ -56,11 +56,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_8k_1rw1r_func_test.py b/compiler/tests/50_riscv_8k_1rw1r_func_test.py index f2861bad..591c96c3 100755 --- a/compiler/tests/50_riscv_8k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_8k_1rw1r_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=2048, @@ -54,11 +54,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/50_riscv_8k_1rw_func_test.py b/compiler/tests/50_riscv_8k_1rw_func_test.py index 22db186e..eb5b75f6 100755 --- a/compiler/tests/50_riscv_8k_1rw_func_test.py +++ b/compiler/tests/50_riscv_8k_1rw_func_test.py @@ -1,19 +1,19 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS @unittest.skip("SKIPPING 50_riscv_func_test") @@ -21,7 +21,7 @@ class riscv_func_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False @@ -30,14 +30,14 @@ class riscv_func_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload - import characterizer + from openram import characterizer reload(characterizer) - from characterizer import functional - from modules import sram_config + from openram.characterizer import functional + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=2048, @@ -56,11 +56,12 @@ class riscv_func_test(openram_test): (fail, error) = f.run() self.assertTrue(fail, error) - globals.end_openram() + openram.end_openram() + # instantiate a copy of the class to actually run the test if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index 2e918eba..f736d222 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -6,7 +6,6 @@ include $(TOP_DIR)/openram.mk ARGS ?= TEST_TECHS ?= scn4m_subm freepdk45 TECHS ?= scn4m_subm freepdk45 sky130 -KEEP ?= false TEST_DIR = $(TOP_DIR)/compiler/tests TEST_SRCS = $(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py))) @@ -122,7 +121,7 @@ $(TEST_BASES): @mkdir -p results/$*/tmp @$(DOCKER_CMD) sh -c ". /home/cad-user/.bashrc && sleep 1 && python3 -u $(OPENRAM_DIR)/$(getfile).py \ -t $(gettech) -k -v $(ARGS) -p $(OPENRAM_DIR)/results/$* > $(OPENRAM_DIR)/results/$*.out 2>&1 && touch $(OPENRAM_DIR)/results/$*.ok || touch $(OPENRAM_DIR)/results/$*.bad" -ifeq ($(KEEP),true) +ifdef KEEP @test -f $(TOP_DIR)/compiler/tests/results/$*.ok && echo "$* ... PASS!" || echo "$* ... FAIL!" else @test -f $(TOP_DIR)/compiler/tests/results/$*.ok && echo "$* ... PASS!" && rm -rf $(TOP_DIR)/compiler/tests/results/$* || echo "$* ... FAIL!" diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index 44c3e774..aa350990 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from globals import OPTS +from openram import OPTS word_size = 1 num_words = 16 diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 4bf0aa8b..0e85d378 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from globals import OPTS +from openram import OPTS word_size = 2 num_words = 16 diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 2b42a914..6af2baa9 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -1,11 +1,11 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from globals import OPTS +from openram import OPTS word_size = 2 num_words = 16 diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py index 6499f20c..16be9d50 100755 --- a/compiler/tests/regress.py +++ b/compiler/tests/regress.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -10,8 +10,7 @@ import re import unittest import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) -import globals +from openram import globals from subunit import ProtocolTestCase, TestProtocolClient from testtools import ConcurrentTestSuite diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index bd4a7aa2..b7b2347d 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -1,17 +1,32 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import unittest import sys, os, glob -from globals import OPTS -import debug import pdb import traceback import time +# FIXME: This is a hack for unit tests running on docker. +try: + import openram +except: + # If openram library isn't found as a python package, + # import it from the $OPENRAM_HOME path. + import importlib.util + OPENRAM_HOME = os.getenv("OPENRAM_HOME") + # Import using spec since the directory can be named something + # other than "openram". + spec = importlib.util.spec_from_file_location("openram", "{}/../__init__.py".format(OPENRAM_HOME)) + module = importlib.util.module_from_spec(spec) + sys.modules["openram"] = module + spec.loader.exec_module(module) + import openram +from openram import debug +from openram import OPTS class openram_test(unittest.TestCase): @@ -47,7 +62,7 @@ class openram_test(unittest.TestCase): tempgds = "{}.gds".format(w.name) w.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) - import verify + from openram import verify result=verify.run_drc(w.name, tempgds, None) if result != 0: @@ -67,7 +82,7 @@ class openram_test(unittest.TestCase): if not OPTS.netlist_only: a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) - import verify + from openram import verify # Run both DRC and LVS even if DRC might fail # Magic can still extract despite DRC failing, so it might be ok in some techs # if we ignore things like minimum metal area of pins @@ -108,7 +123,7 @@ class openram_test(unittest.TestCase): a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) - import verify + from openram import verify result=verify.run_pex(a.name, tempgds, tempspice, final_verification=False) if result != 0: self.fail("PEX ERROR: {}".format(a.name)) @@ -139,7 +154,7 @@ class openram_test(unittest.TestCase): Reset everything after each test. """ # Reset the static duplicate name checker for unit tests. - from base import hierarchy_design + from openram.base import hierarchy_design hierarchy_design.name_map=[] def check_golden_data(self, data, golden_data, error_tolerance=1e-2): @@ -167,7 +182,7 @@ class openram_test(unittest.TestCase): def isclose(self, key, value, actual_value, error_tolerance=1e-2): """ This is used to compare relative values. """ - import debug + from openram import debug relative_diff = self.relative_diff(value, actual_value) check = relative_diff <= error_tolerance if check: @@ -215,7 +230,7 @@ class openram_test(unittest.TestCase): """ import re - import debug + from openram import debug numeric_const_pattern = r""" [-+]? # optional sign @@ -294,7 +309,7 @@ class openram_test(unittest.TestCase): def isdiff(self, filename1, filename2): """ This is used to compare two files and display the diff if they are different.. """ - import debug + from openram import debug import filecmp import difflib check = filecmp.cmp(filename1, filename2) @@ -338,7 +353,7 @@ def header(filename, technology): print("|=========" + tst.center(60) + "=========|") print("|=========" + technology.center(60) + "=========|") print("|=========" + filename.center(60) + "=========|") - from globals import OPTS + from openram import OPTS if OPTS.openram_temp: print("|=========" + OPTS.openram_temp.center(60) + "=========|") print("|==============================================================================|") diff --git a/compiler/uniquifyGDS.py b/compiler/uniquifyGDS.py deleted file mode 100755 index 8eddce3d..00000000 --- a/compiler/uniquifyGDS.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 - -import sys -from gdsMill import gdsMill - -if len(sys.argv) < 4: - print("Script to prefix every instance and structure with the root cell name to provide unique namespace, but skip cells that begin with the library prefix.") - print("Usage: {0} in.gds out.gds".format(sys.argv[0])) - sys.exit(1) - -gds_file = sys.argv[2] -gds = gdsMill.VlsiLayout() -reader = gdsMill.Gds2reader(gds) -reader.loadFromFile(gds_file) - -gds.uniquify(prefix_name=sys.argv[1]) - -writer = gdsMill.Gds2writer(gds) -writer.writeToFile(sys.argv[3]) diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index b4a3f254..5224e769 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -15,12 +15,11 @@ run_pex, repsectively. If there is an error, they should abort and report the er If not, OpenRAM will continue as if nothing happened! """ -import debug -from globals import OPTS -from globals import get_tool -from tech import drc_name -from tech import lvs_name -from tech import pex_name +from openram import debug +from openram.tech import drc_name +from openram.tech import lvs_name +from openram.tech import pex_name +from openram import OPTS, get_tool debug.info(1, "Initializing verify...") if not OPTS.check_lvsdrc: diff --git a/compiler/verify/assura.py b/compiler/verify/assura.py index 64c482a1..bf5274fe 100644 --- a/compiler/verify/assura.py +++ b/compiler/verify/assura.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -25,12 +25,11 @@ drc["lvs_subcircuits"] variable, and additional options must be inserted in the runset. """ - import os import re -from run_script import * -import debug -from globals import OPTS +from openram import debug +from openram.verify.run_script import * +from openram import OPTS # Keep track of statistics num_drc_runs = 0 @@ -39,7 +38,7 @@ num_pex_runs = 0 def write_drc_script(cell_name, gds_name, extract, final_verification, output_path): - from tech import drc + from openram.tech import drc drc_rules = drc["drc_rules"] drc_runset = output_path + cell_name + ".rsf" drc_log_file = "{0}{1}.log".format(OPTS.openram_temp, name) @@ -108,7 +107,7 @@ def run_drc(name, gds_name, final_verification=False): def write_lvs_script(cell_name, gds_name, sp_name, final_verification, output_path): - from tech import drc + from openram.tech import drc lvs_rules = drc["lvs_rules"] lvs_runset = output_path + name + ".rsf" # The LVS compare rules must be defined in the tech file for Assura. diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 32c5c5a9..54ffea80 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -16,11 +16,10 @@ Calibre means pointing the code to the proper DRC and LVS rule files. """ - import os import re -import debug -from globals import OPTS +from openram import debug +from openram import OPTS from .run_script import run_script # Keep track of statistics @@ -36,7 +35,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification=False, out if not output_path: output_path = OPTS.openram_temp - from tech import drc + from openram.tech import drc drc_rules = drc["drc_rules"] drc_runset = { @@ -77,7 +76,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out if not output_path: output_path = OPTS.openram_temp - from tech import drc + from openram.tech import drc lvs_rules = drc["lvs_rules"] lvs_runset = { 'lvsRulesFile': lvs_rules, @@ -151,7 +150,7 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu run_drc(cell_name, gds_name, sp_name) run_lvs(cell_name, gds_name, sp_name) - from tech import drc + from openram.tech import drc pex_rules = drc["xrc_rules"] pex_runset = { 'pexRulesFile': pex_rules, diff --git a/compiler/verify/klayout.py b/compiler/verify/klayout.py index 73cec474..e97b0d88 100644 --- a/compiler/verify/klayout.py +++ b/compiler/verify/klayout.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -10,12 +10,11 @@ This is a DRC/LVS/PEX interface file for klayout. """ - import os import re import shutil -import debug -from globals import OPTS +from openram import debug +from openram import OPTS from .run_script import * # Keep track of statistics diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index a3e0e511..a19f235d 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -19,12 +19,11 @@ We obtained this file from Qflow ( http://opencircuitdesign.com/qflow/index.html and include its appropriate license. """ - import os import re import shutil -import debug -from globals import OPTS +from openram import debug +from openram import OPTS from .run_script import * # Keep track of statistics num_drc_runs = 0 @@ -96,12 +95,12 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa # Flatten the transistors # Bug in Netgen 1.5.194 when using this... try: - from tech import blackbox_cells + from openram.tech import blackbox_cells except ImportError: blackbox_cells = [] try: - from tech import flatglob + from openram.tech import flatglob except ImportError: flatglob = [] f.write("gds readonly true\n") diff --git a/compiler/verify/none.py b/compiler/verify/none.py index 8385be11..96571b62 100644 --- a/compiler/verify/none.py +++ b/compiler/verify/none.py @@ -1,15 +1,15 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # """ This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools. - """ -import debug + +from openram import debug # Only print the warning once. drc_warned = False diff --git a/compiler/verify/run_script.py b/compiler/verify/run_script.py index 1c4cc0dd..e3d689d3 100644 --- a/compiler/verify/run_script.py +++ b/compiler/verify/run_script.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -10,10 +10,10 @@ Some baseline functions to run scripts. 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diff --git a/docs/assets/images/routing/power_routing.png b/docs/assets/images/routing/power_routing.png new file mode 100644 index 00000000..db320237 Binary files /dev/null and b/docs/assets/images/routing/power_routing.png differ diff --git a/docs/source/FAQ.md b/docs/source/FAQ.md new file mode 100644 index 00000000..a515b17a --- /dev/null +++ b/docs/source/FAQ.md @@ -0,0 +1,38 @@ +### [Go Back](./index.md#table-of-contents) + +# Frequently Asked Questions + +## What to do if OpenRAM encounters an error? + +When OpenRAM runs, it puts files in a temporary directory that is +shown in the banner at the top. Like: +``` + /tmp/openram_mrg_18128_temp/ +``` +This is where simulations and DRC/LVS get run so there is no network +traffic. The directory name is unique for each person and run of +OpenRAM to not clobber any files and allow simultaneous runs. If it +passes, the files are deleted. If it fails, you will see these files: ++ `temp.gds` is the layout (.mag files too if using SCMOS) ++ `temp.sp` is the netlist ++ `test1.drc.err` is the std err output of the DRC command ++ `test1.drc.out` is the standard output of the DRC command ++ `test1.drc.results` is the DRC results file ++ `test1.lvs.err` is the std err output of the LVS command ++ `test1.lvs.out` is the standard output of the LVS command ++ `test1.lvs.results` is the DRC results file + +Depending on your DRC/LVS tools, there will also be: ++ `run\_drc.sh` is a script to run DRC ++ `run\_ext.sh` is a script to run extraction ++ `run\_lvs.sh` is a script to run LVS + +If DRC/LVS fails, the first thing is to check if it ran in the `.out` and +`.err` file. This shows the standard output and error output from +running DRC/LVS. If there is a setup problem it will be shown here. + +If DRC/LVS runs, but doesn't pass, you then should look at the `.results` +file. If the DRC fails, it will typically show you the command that was used +to run Calibre or Magic+Netgen. + + diff --git a/docs/source/architecture.md b/docs/source/architecture.md new file mode 100644 index 00000000..99dea80b --- /dev/null +++ b/docs/source/architecture.md @@ -0,0 +1,25 @@ +### [Go Back](./index.md#table-of-contents) + +# Architecture +This page of the documentation explains the architecture of OpenRAM. + + + +## Table of Contents +1. [SRAM Architecture](#sram-architecture) + + + +## SRAM Architecture +* Bit-cell Array + * Multiport Bitcells +* Each port: + * Address Decoder(s) + * Wordline Driver(s) + * Column Multiplexer(s) + * Bitline Precharge(s) + * Sense Amplifier(s) + * Write Driver(s) + * Control Logic with Replica Bitline + +![OpenRAM SRAM Architecture](../assets/images/architecture/sram_architecture.png) \ No newline at end of file diff --git a/docs/source/base_data_structures.md b/docs/source/base_data_structures.md new file mode 100644 index 00000000..72083e99 --- /dev/null +++ b/docs/source/base_data_structures.md @@ -0,0 +1,72 @@ +### [Go Back](./index.md#table-of-contents) + +# Base Data Structures +This page of the documentation explains the base data structures of OpenRAM. + + + +## Table of Contents +1. [Design Classes](#design-classes) +1. [Base Class Inheritance](#base-class-inheritance) +1. [Parameterized Transistor](#parameterized-transistor-ptx-or-pfinfet) +1. [Parameterized Cells](#parameterized-cells) + + + +## Design Classes + + +* SPICE and GDS2 Interfaces + * Custom cells (read GDS and SPICE) + * Generated cells (creates GDS and SPICE "on the fly") +* Netlist functions + * Add (directional) pins + * Add and connect instances + +* Layout functions + * Place instances + * Add wires, routes, vias + * Channel and Power router +* Verification functions (wrap around DRC and LVS tools) + + + +## Base Class Inheritance +```mermaid +flowchart TD + A[design.py \n\n General design and helper DRC constants] --> B[hierarchy_design.py \n\n DRC/LVS functions] + B --> C["hierarchy_spice.py \n\n Netlist related functionality"] + B --> D["hierarchy_layout.py \n\n Layout related functionality"] + C --> E["Functions: \n add_pins \n add_inst"] + C --> F["sp_read \n sp_write \n Power data \n Delay data"] + D --> G["Functions: \n add_{layout_pin,rect,...} \n place_inst \n create_channel_route \n etc."] + D --> H["gds_read \n gds_write \n get_blockages \n etc."] +``` + + + +## Parameterized Transistor (ptx or pfinfet) + + +* Creates variable size/finger nmos or pmos transistor + * Optional gate and source/drain contacts in naive way + * Not optimal layout, but "good enough" + * Offset (0,0) is lower-left corner of active area +* Size/fingers effect on size must be estimated elsewhere perhaps by trying configurations + + + +## Parameterized Cells + + +Dynamically generated cells (in `$OPENRAM_HOME/pgates`) +* Not the most efficient layouts but "ok" +* Try to use restrictive design rules to keep them portable +* Transistors + * `ptx`, `pfinfet` +* Logic gates + * `pinv`, `pnand2`, `pnand3`, `pnor2` +* Buffer/drivers + * `pbuf`, `pinvbuf`, `pdriver` +* SRAM Logic + * `precharge`, `single_level_column_mux` diff --git a/docs/source/basic_setup.md b/docs/source/basic_setup.md new file mode 100644 index 00000000..90cc773e --- /dev/null +++ b/docs/source/basic_setup.md @@ -0,0 +1,113 @@ +### [Go Back](./index.md#table-of-contents) + +# Basic Setup +This page shows the basic setup for using OpenRAM. + + + +## Table of Contents +1. [Dependencies](#dependencies) +1. [OpenRAM Library](#openram-library) +1. [Docker](#docker) +1. [Environment](#environment) +1. [Sky130 Setup](#sky130-setup) + + + +## Dependencies +Please see the Dockerfile for the required versions of tools. + +In general, the OpenRAM compiler has very few dependencies: ++ Docker ++ Make ++ Python 3.6 or higher ++ Various Python packages (pip install -r requirements.txt) ++ Git + + + +## OpenRAM Library +OpenRAM is available as a Python library. There are a few ways to install it: + ++ Install using Makefile (you need to clone the repo): +``` +git clone git@github.com:VLSIDA/OpenRAM.git +cd OpenRAM +make library +``` + ++ Install the latest _dev_ version: +``` +pip3 install git+ssh://git@github.com/VLSIDA/OpenRAM.git@dev +``` + + +## Docker +We have a [docker setup](../../docker) to run OpenRAM. To use this, you should run: +``` +cd OpenRAM/docker +make build +``` +This must be run once and will take a while to build all the tools. If you have the +OpenRAM library installed, you can also run the docker setup from the package +installation directory. + + + +## Environment + +If you haven't installed the OpenRAM library or you want to use a different OpenRAM installation, +you can set two environment variables: ++ OPENRAM\_HOME should point to the compiler source directory. ++ OPENRAM\_TECH should point to one or more root technology directories (colon separated). + +If you have the library installed and OPENRAM\_HOME set, the library will use the installation on +the OPENRAM\_HOME path. + +If you don't have the library, you should also add OPENRAM\_HOME to your PYTHONPATH. This is not +needed if you have the library. + +You can add these environment variables to your `.bashrc`: +``` + export OPENRAM_HOME="$HOME/OpenRAM/compiler" + export OPENRAM_TECH="$HOME/OpenRAM/technology" + export PYTHONPATH=$OPENRAM_HOME +``` + +Note that if you want symbols to resolve in your editor, you may also want to add the specific technology +directory that you use and any custom technology modules as well. For example: +``` + export PYTHONPATH="$OPENRAM_HOME:$OPENRAM_TECH/sky130:$OPENRAM_TECH/sky130/custom" +``` + +We include the tech files necessary for [SCMOS] SCN4M\_SUBM, +[FreePDK45]. The [SCMOS] spice models, however, are +generic and should be replaced with foundry models. You may get the +entire [FreePDK45 PDK here][FreePDK45]. + + + +### Sky130 Setup + +To install [Sky130], you must have open\_pdks installed in $PDK\_ROOT. We highly recommend that you +use the version tagged in the Makefile as others have not been verified. +To install this automatically, you can run: +``` +cd $HOME/OpenRAM +make pdk +``` + +Then you must also install the [Sky130] SRAM build space with the appropriate cell views into the OpenRAM technology directory +by running: +``` +cd $HOME/OpenRAM +make install +``` + +You can also run these from the package installation directory if you have the OpenRAM library. + + + +[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf +[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents +[Sky130]: https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git diff --git a/docs/source/basic_usage.md b/docs/source/basic_usage.md new file mode 100644 index 00000000..b9f5f468 --- /dev/null +++ b/docs/source/basic_usage.md @@ -0,0 +1,224 @@ +### [Go Back](./index.md#table-of-contents) + +# Basic Usage +This page of the documentation explains the basic usage of OpenRAM. + + + +## Table of Contents +1. [Environment Variable Setup](#environment-variable-setup-assuming-bash) +1. [Script Usage (with library)](#script-usage-with-library) +1. [Command Line Usage (with library)](#command-line-usage-with-library) +1. [Command Line Usage (without library)](#command-line-usage-without-library) +1. [Configuration Files](#configuration-files) +1. [Common Configuration File Options](#common-configuration-file-options) +1. [Output Files](#output-files) +1. [Data Sheets](#data-sheets) + + + +## Environment Variable Setup (assuming bash) +> **Note**: This is optional if you have the OpenRAM library. See [basic setup](./basic_setup.md#go-back) for details. +* OPENRAM\_HOME defines where the compiler directory is + * ```export OPENRAM_HOME="$HOME/openram/compiler"``` +* OPENRAM_TECH defines list of paths where the technologies exist + * `export OPENRAM_TECH="$HOME/openram/technology"` + * Colon separated list so you can have private technology directories +* Must also have any PDK related variables set up +* Add compiler to `PYTHONPATH` + * `export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"` + + + +## Script Usage (with library) +If you have the library installed, you can use OpenRAM in any Python script. You can import "openram" as follows: +```python +import openram +openram.init_openram("myconfig.py") # Config files are explained on this page +# Now you can use modules from openram +from openram import tech +... +``` + +Note that you need to initalize OpenRAM so that the modules are imported properly. You can also look +at [sram_compiler.py](../../sram_compiler.py) as an example on how to use "openram." + +If you want to pass custom configuration when generating an SRAM, you can use the `sram_config` class. +```python +import openram +openram.init_openram("myconfig.py") + +from openram import sram_config +c = sram_config(...) + +from openram import sram +s = sram(sram_config=c, + name="custom_name") + +s.save() + +openram.end_openram() +``` + + +## Command Line Usage (with library) +You can run OpenRAM from the command line using the [sram_compiler.py](../../sram_compiler.py) script that is +included in the library's installation. You can find the package directory on a path like: +``` +/home/mrg/.local/lib/python3.8/site-packages/openram +``` + +Alternatively, you can run the following command to find that path: +``` +echo -e "import os\nimport openram\nprint(os.path.dirname(openram.__file__))" | python3 - +``` + +You can continue with following section for more details. + + +## Command Line Usage (without library) +Once you have defined the environment, you can run OpenRAM from the command line +using a single configuration file written in Python. + +For example, create a file called *myconfig.py* specifying the following +parameters for your memory: +```python +# Data word size +word_size = 2 +# Number of words in the memory +num_words = 16 + +# Technology to use in $OPENRAM_TECH +tech_name = "scn4m_subm" + +# You can use the technology nominal corner only +nominal_corner_only = True +# Or you can specify particular corners +# Process corners to characterize +# process_corners = ["SS", "TT", "FF"] +# Voltage corners to characterize +# supply_voltages = [ 3.0, 3.3, 3.5 ] +# Temperature corners to characterize +# temperatures = [ 0, 25 100] + +# Output directory for the results +output_path = "temp" +# Output file base name +output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) + +# Disable analytical models for full characterization (WARNING: slow!) +# analytical_delay = False + +``` + +You can then run OpenRAM by executing: +``` +python3 $OPENRAM_HOME/../sram_compiler.py myconfig +``` +You can see all of the options for the configuration file in +$OPENRAM\_HOME/options.py + +To run designs in Docker, it is suggested to use, for example: +``` +cd OpenRAM/macros +make example_config_scn4m_subm +``` + +* Common arguments: + * `-t` specify technology (scn4m_subm or scmos or freepdk45) + * `-v` increase verbosity of output + * `-n` don't run DRC/LVS + * `-c` perform simulation-based characterization + * `-d` don't purge /tmp directory contents + + + +## Configuration Files +* Memories are created using a Python configuration file to replicate results + * No YAML, JSON, etc. +* Complete configuration options are in `$OPENRAM_HOME/options.py` +* Some options can be specified on the command line as well + * Not recommended for replicating results +* Example configuration file: + ```python + # Data word size + word_size = 2 + # Number of words in the memory + num_words = 16 + + # Technology to use in $OPENRAM_TECH + tech_name = "scn4m_subm" + # Process corners to characterize + process_corners = [ "TT" ] + # Voltage corners to characterize + supply_voltages = [ 3.3 ] + # Temperature corners to characterize + temperatures = [ 25 ] + + # Output directory for the results + output_path = "temp" + # Output file base name + output_name = "sram_16x2" + + # Disable analytical models for full characterization (WARNING: slow!) + # analytical_delay = False + + # To force this to use magic and netgen for DRC/LVS/PEX + # Could be calibre for FreePDK45 + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" + ``` + + + +## Common Configuration File Options +* Characterization corners + * `supply_voltages = [1.7, 1.8, 1.9]` + * `temperatures = [25, 50, 100]` + * `process_corners = ["SS", "TT", "FF"]` +* Do not generate layout + * `netlist_only = True` +* Multi-port options + * `num_rw_ports = 1` + * `num_r_ports = 1` + * `num_w_ports = 0` +* Customized module or bit cell + * `bitcell = "bitcell_1rw_1r"` + * `replica_bitcell = "replica_bitcell_1rw_1r"` +* Enable simulation characterization + > **Warning**: Slow! + * `analytical_delay = False` +* Output name and location + * `output_path = "temp"` + * `output_name = "sram_32x256"` +* Force tool selection (should match the PDK!) + * `drc_name = "magic"` + * `lvs_name = "netgen"` + * `pex_name = "magic"` +* Include shared configuration options using Python imports + * `from corners_freepdk45 import *` + + + +## Output Files +The output files are placed in the `output_dir` defined in the configuration file. + +The base name is specified by `output_name` and suffixes are added. + +The final results files are: +* GDS (.gds) +* SPICE (.sp) +* Verilog (.v) +* P&R Abstract (.lef) +* Liberty (multiple corners .lib) +* Datasheet (.html) +* Log (.log) +* Configuration (.py) for replication of creation + + + +## Data Sheets +![Datasheet 1](../assets/images/basic_usage/datasheet_1.png) +![Datasheet 2](../assets/images/basic_usage/datasheet_2.png) +![Datasheet 3](../assets/images/basic_usage/datasheet_3.png) diff --git a/docs/source/bitcells.md b/docs/source/bitcells.md new file mode 100644 index 00000000..92c5709b --- /dev/null +++ b/docs/source/bitcells.md @@ -0,0 +1,40 @@ +### [Go Back](./index.md#table-of-contents) + +# Bitcells +This page of the documentation explains the bitcells supported by OpenRAM. + + + +## Table of Contents +1. [Multiport Bitcells](#multiport-bitcells) +1. [Relative Bitcell Sizes](#relative-bitcell-sizes-035um-scmos) +1. [Thin SRAM Bitcells](#thin-sram-bitcells-130nm) + + + +## Multiport Bitcells +* Based on 6T SRAM cell + * Standard read-write + * Isolated read-only ports + * Write-only port (not sized for reads) +* Can accommodate foundry bitcells + +![Multiport Bitcells](../assets/images/bitcells/multiport_bitcells.png) + + + +## Relative Bitcell Sizes (0.35um SCMOS) +| | | | +| :-----------------------------------------------: | :------------------------------------------------: | :--------------------------------------------------: | +| Standard 6T (1rw) 6.8um x 9.2um | Isolated Read 10T (1rw, 1r) 10.9um x 13.9um | DFF 21.9um x 21.2um (from OSU standard cell library) | + + + +## Thin SRAM Bitcells (130nm) +| | | | | +| :--------------------------------------------------------: | :------------------------------------------------------: | :-----------------------------------------------------------------: | :-------------------------------------------------------------: | +| Single Port 1.2um x 1.58um | Dual Port 2.40um x 1.58um | Single Port (w/ straps & taps) 2.49um x 1.58um | Dual Port (w/ straps & taps) 3.12um x 1.97um | + +| | +| :----------------------------------------------------------: | +| DFF (for reference) 5.83um x 7.07 um | diff --git a/docs/source/characterization.md b/docs/source/characterization.md new file mode 100644 index 00000000..60adc74a --- /dev/null +++ b/docs/source/characterization.md @@ -0,0 +1,178 @@ +### [Go Back](./index.md#table-of-contents) + +# Characterization +This page of the documentation explains the characterization of OpenRAM. + + + +## Table of Contents +1. [Characterization Overview](#characterization-overview) +1. [Characterizer Organization](#characterizer-organization) +1. [Characterization Options](#characterization-options) +1. [Characterization Measurements](#characterization-measurements) +1. [Analytical Characterization](#analytical-characterization) +1. [Multiport Characterization](#multiport-characterization) +1. [Characterizer Unit Test Use](#characterizer-unit-test-use) +1. [Functional Simulation](#functional-simulation) +1. [Power/Delay Characterization](#powerdelay-characterization) +1. [Timing Graph](#timing-graph) +1. [Graph Creation Example: Buffer](#graph-creation-example-buffer) +1. [Graph Module Exclusion](#graph-module-exclusion) +1. [Timing Measurement Checks](#timing-measurement-checks) + + + +## Characterization Overview +Measures the timing/power through SPICE simulation: +* Generates the SPICE stimulus: The stimulus is written in standard SPICE format and can be used with any simulator that supports this. +* Runs the circuit simulations: To produce the average power, setup/hold times, and timing delay of the memory design. +* Parses the simulator's output: The setup time, hold time, and delay are found using a bidirectional search technique. +* Produces the output in a Liberty (.lib) file. + + + +## Characterizer Organization +* Core Modules + * `delay.py` - Generates the delays and power of input SRAM and corner + * `setup_hold.py` - Generates setup and hold timing of DFFs by corner + * `lib.py` - Characterizes SRAM and builds Liberty file + * `stimuli.py` - Generates SPICE stimulus file for characterization +* Auxiliary Modules + * `simulation.py` - Base class for SRAM characterization modules + * `trim_spice.py` - Removes portions of SRAM SPICE to speedup simulation + * `measurements.py` - Contains classes to aid SPICE measurements + * `char_utils.py` - Contains common functions used during characterization + * `logical_effort.py` - Helper class for analytical delay model +* Testing Support Modules + * Other modules are derivatives of the simulation module used in the unit tests + + + +## Characterization Options +* Characterization by Configuration File + * The process, voltage, and temperature (PVT) for characterization are defined in the config file. + * Running OpenRAM generates a Liberty (.lib) file for every corner characterized. + * Delays, slews, power determined for each input slew and outputs load combination in config file. +* OpenRAM Characterization Mode + * Supports analytical and SPICE based characterization + * Analytical characterization is default + * SPICE characterization enabled with -c flag (requires SPICE simulator) + + + +## Characterization Measurements +* Characterization is performed primarily to generate tables in .lib file + * cell\_rise/cell\_fall - Delay of from negative clock edge to DOUT when reading a 1 or 0 respectively + * rise\_transition/fall\_transition - Slew of DOUT when read 1 or 0 respectively + * Setup and hold time for inputs (setup\_rising, hold\_rising) + * Total power and leakage power + * Delays and slews and intended to be independent of clock period. + * Fall delays are copied to rise delays after characterization* +* Characterizer can help with debugging or optimization + * Delay characterizer also produces Sense Amp Enable Timing to help debug read failures. + * Delay class can edited or can be base class if other measurements are wanted. +> **Note**: Rise delays are dependent on the clock period if measured from negative clock edge due to precharge. + + + +## Analytical Characterization +* Delay + * Assumes a worst case delay through decoder, word line, and bit lines + * Calculates RC delay at each stage using parameters for handmade cells, unit capacitances, and unit resistances which are defined in the technology setup + * Output slews are estimated based on delays + * Wire delays only estimated for bitline delay +* Power + * Dynamic power at each stage calculated using $C * V^2 * frequency$ + * Leakage power estimated with parameters in technology setup +* Corners add linear variations in delay and power + + + +## Multiport Characterization +* Supports any port configuration specified by the configuration file + * Any number of Read, Write, and Read/Write ports + * Any custom bitcells may require modifications for characterization +* Characterization Algorithm + * Feasible period found for each port + * Common minimum period is found for all ports + * Power and delay is characterized on each port +* Characterization Runtime + * Ports are characterized separately for accuracy + * Runtime increases linearly with ports and can be slow. + + + +## Characterizer Unit Test Use +* OpenRAM will use the characterizer to generate data for .lib by default +* Characterizer modules can be instantiated separately from lib.py to generate and test data + * Example: `21_ngspice_delay_test.py` + * Delay module generates data to compare against previously generated data to error check any recent OpenRAM changes having a large effect on the delay +* Delay/Simulation module can be used as base class and altered to include custom measurements + + + +## Functional Simulation +* Assumes uninitialized memory +* Random operations + * Uses multiple ports when available + * Read, write, or noop + * Random address + * Random data +* Memory checks + * Uses standard CMOS noise margins + * Compares read with last write (or feed-through value if being written) + + + +## Power/Delay Characterization +* Prunes unused portions of circuit for run-time +* Setup time, hold time, and delay are found using a bidirectional search. + * Finds a feasible period + * Iterates until convergence +* Dynamic and leakage measured +* Output saved in Liberty (.lib) file. + * Uses NLDM + * Wish list: CCS + + + +## Timing Graph +* OpenRAM has SPICE like modules and instances +* A timing graph is created using the SPICE netlist, names and paths through lower level modules. +* Graph used in characterizer for debugging timing issues associated with the Sense Amp Enable + + + +## Graph Creation Example: Buffer +![Buffer 1](../assets/images/characterization/buffer_1.png) +* SPICE instantiated module (vdd, gnd excluded from graph) +* Xbuf1 A Z vdd gnd Buffer +* Base module has its own naming for ports and internal signals + +![Buffer 2](../assets/images/characterization/buffer_2.png) +* Node names reduced to top-most SPICE level with internal signals maintained. +* Internal modules determine edges between nodes + +![Buffer 3](../assets/images/characterization/buffer_3.png) +* Most lower level modules (gates, PTX, FF, etc) determine edges by connecting every input to every output by default. +* Custom timing paths can be overridden in any module + + + +## Graph Module Exclusion +* Modules can be excluded from the graph before it's built +* This can help trim timing paths that are known to not affect the overall timing +![Graph Module Exclusion](../assets/images/characterization/exclusion.png) + +| | | +| :-------------------------------------------------------------------------: | :----------------------------------------------------------------------------: | +| Graph without exclusion | Graph with exclusion | + + + +## Timing Measurement Checks +In addition to measurements done for characterization. Several measurements are done to help debug memory failures. +* Bitline measurements - Voltage of bitlines measured the checked to have at least a 10% difference +* Bitcell Measurements - Voltage measured on internal storage of cells and check that they match the operation. +* Output voltage measurements - Output voltage (`DOUT`) checked at end of cycle so it matches operation. +* Sense Amp Enable Timing - Delay of `S_EN` should not exceed a half-period diff --git a/docs/source/control_logic.md b/docs/source/control_logic.md new file mode 100644 index 00000000..f760e379 --- /dev/null +++ b/docs/source/control_logic.md @@ -0,0 +1,100 @@ +### [Go Back](./index.md#table-of-contents) + +# Control Logic and Timing +This page of the documentation explains the control logic and timing of OpenRAM. + + + +## Table of Contents +1. [Read Timing](#read-timing) +1. [Write Timing](#write-timing) +1. [External Control Signals](#external-control-signals) +1. [Internal Control Signals](#internal-control-signals) +1. [Replica Bitline (RBL)](#replica-bitline-rbl) +1. [Internal Control Signals Diagram (Read)](#internal-control-signals-diagram-read) +1. [Internal Control Signals Diagram (Write)](#internal-control-signals-diagram-write) +1. [Clock Distribution](#clock-distribution) + + + +## Read Timing +![Read Timing](../assets/images/control_logic/read_timing.png) + + + +### Read Timing Simulation +![Read Timing Simulation](../assets/images/control_logic/read_simulation.png) + + + +## Write Timing +![Write Timing](../assets/images/control_logic/write_timing.png) + + + +### Write Timing Simulation +![Write Timing Simulation](../assets/images/control_logic/write_simulation.png) + + + +## External Control Signals +* Behaves as a synchronous register interface + * Address and data captured on positive edge + * Data is available after the negative edge (before next positive edge) + * Clock is used for internal control generation +* Clock cycle + * Clock high: capture inputs + precharge + decode + * Clock low: read/write +* Reads and writes on multiple ports to the same address in the same cycle "feed through" but the noise margins of the bitcell must be able to handle this + + + +## Internal Control Signals +* Sense Enable (`s_en`) -- Active high sense amp enable from Replica Bit Line (RB) + * RBL input: `rbl_wl = gated_clk_bar & we_bar` + * Delayed RBL output: `pre_s_en = DELAY(rbl_bl)` + * Buffered enable: `s_en = BUF(pre_s_en)` +* Write Driver Enable (`w_en`) -- Active high write driver enable + * `w_en = we` + * `we` is directly from control flops +* Precharge Enable Bar (`p_en_bar`) -- Active low enable of precharge + * `p_en_bar = !(gated_clk_bar)` + * Active for writes as well to prevent half select destruction +* Word line enable (`wl_en`) -- Active high word line enable + * `wl_en = BUF(gated_clk_bar)` + + + +## Replica Bitline (RBL) + + +* Determines when to start sensing by replicating a bitcell array column +* Replica Bitline Column (RBC) matches transition of column + * `rbl_bl = RBC(rbl_wl)` +* Delay Line delays the input signal to match word line driver + * `pre_s_en = DELAY(rbl_bl)` +* Buffer drives `s_en` signal to sense amps + + + +## Internal Control Signals Diagram (Read) +![Internal Control Signals (Read)](../assets/images/control_logic/internal_signals_read.png) + + + +## Internal Control Signals Diagram (Write) +![Internal Control Signals (Write)](../assets/images/control_logic/internal_signals_write.png) + + + +## Clock Distribution +* External clock (`clk`) +* Buffered clock (`clk_buf`) drives all DFFs in the design + * `clk_buf = BUF(clk)` +* Buffered clock bar (`clk_bar`) used in control logic + * `clk_bar = INV(clk_buf)` +* Gated Clocks (`gated_clk` and `gated_clk_bar`) used in control logic + * This is LOW when disabled + * `gated_clk_bar = cs && clk_bar` + * This is LOW when disabled + * `gated_clk = cs && clk_buf` diff --git a/docs/source/debug.md b/docs/source/debug.md new file mode 100644 index 00000000..73cc31db --- /dev/null +++ b/docs/source/debug.md @@ -0,0 +1,179 @@ +### [Go Back](./index.md#table-of-contents) + +# Debugging and Unit Testing +This page of the documentation explains the debugging and unit testing of OpenRAM. + + + +## Table of Contents +1. [Unit Tests](#unit-tests) +1. [Unit Test Organization](#unit-test-organization) +1. [Running Unit Tests](#running-unit-tests) +1. [Successful Unit Tests](#successful-unit-tests) +1. [Debugging Unsuccessful Unit Tests](#debugging-unsuccessful-unit-tests-or-sram_compilerpy) +1. [Temporary Output Files](#temporary-output-files) + + + +## Unit Tests +OpenRAM has the set of thorough regression tests implemented with the Python unit test framework: +* Unit tests allow users to add features without worrying about breaking functionality. +* Unit tests guide users when porting to new technologies. +* Every sub-module has its own regression test. +* There are regression tests for memory functionality, library cell verification, timing verification, and technology verification. + + + +## Unit Test Organization +* `00_code_format_test.py` does basic lint checking. +* `01_library_drc_test.py` checks DRC of all library cells for the technology. +* `02_library_lvs_test.py` checks LVS of all library cells for the technology. +* `03_*_test.py` checks DRC and LVS of wires and transistors classes. +* `04_*_test.py` checks DRC and LVS of parameterized cells. +* `05-19_*_test.py` checks DRC and LVS of module cells (moving upward in hierarchy with numbers) +* `20_*_test.py` check DRC and LVS of full SRAM layouts with various configurations. +* `21_*_test.py` checks timing of full SRAMs and compares (with tolerance) to precomputed result. + > **Note**: These tests may fail using different simulators due to the tolerance level. +* `22_*_test.py` checks functional simulation of full SRAMs with various configurations. +* `23-25_*_test.py` checks lib, lef, and verilog outputs using diff. +* `30_openram_test.py` checks command-line interface and whether output files are created. + + + +## Running Unit Tests + +Regression testing performs a number of tests for all modules in OpenRAM. +From the unit test directory ($OPENRAM\_HOME/tests), +use the following command to run all regression tests: + +``` +cd OpenRAM/compiler/tests +make -j 3 +``` +The -j can run with 3 threads. By default, this will run in all technologies. + +To run a specific test in all technologies: +``` +cd OpenRAM/compiler/tests +make 05_bitcell_array_test +``` +To run a specific technology: +``` +cd OpenRAM/compiler/tests +TECHS=scn4m_subm make 05_bitcell_array_test +``` + +To increase the verbosity of the test, add one (or more) -v options and +pass it as an argument to OpenRAM: +``` +ARGS="-v" make 05_bitcell_array_test +``` + +Unit test results are put in a directory: +``` +OpenRAM/compiler/tests/results// +``` +If the test fails, there will be a tmp directory with intermediate results. +If the test passes, this directory will be deleted to save space. +You can view the .out file to see what the output of a test is in either case. +* Tests can be run in the `$OPENRAM_HOME/tests` directory +* Command line arguments + * `-v` for verbose + * `-t` freepdk45 for tech + * `-d` to preserve /tmp results (done automatically if test fails) +* Individual tests + * `01_library_drc_test.py` +* All tests + * `regress.py` + + +## Successful Unit Tests +```console +user@host:/openram/compiler/tests$ ./regress.py + ______________________________________________________________________________ +|==============================================================================| +|========= Running Test for: =========| +|========= scn4m_subm =========| +|========= ./regress.py =========| +|========= /tmp/openram_mrg_13245_temp/ =========| +|==============================================================================| +runTest (00_code_format_check_test.code_format_test) ... ok +runTest (01_library_drc_test.library_drc_test) ... ok +runTest (02_library_lvs_test.library_lvs_test) ... ok +runTest (03_contact_test.contact_test) ... ok +runTest (03_path_test.path_test) ... ok +. +. +. +``` +```console +user@host:/openram/compiler/tests$ ./03_ptx_1finger_nmos_test.py + ______________________________________________________________________________ +|==============================================================================| +|========= Running Test for: =========| +|========= scn4m_subm =========| +|========= ./03_ptx_1finger_nmos_test.py =========| +|========= /tmp/openram_mrg_13750_temp/ =========| +|==============================================================================| +. +---------------------------------------------------------------------- +Ran 1 test in 0.596s + +OK +``` + + + +## Debugging Unsuccessful Unit Tests (or sram\_compiler.py) +* You will get an ERROR during unit test and see a stack trace +* Examine the temporary output files in the temp directory (/tmp/mydir) +```console + _____________________________________________________________________________ +|==============================================================================| +|========= Running Test for: =========| +|========= scn4m_subm =========| +|========= ./04_pinv_10x_test.py =========| +|========= /tmp/mydir =========| +|==============================================================================| +ERROR: file magic.py: line 174: DRC Errors pinv_0 2 +F +====================================================================== +FAIL: runTest (__main__.pinv_test) +---------------------------------------------------------------------- +Traceback (most recent call last): + File "./04_pinv_10x_test.py", line 22, in runTest + self.local_check(tx) + File "/Users/mrg/openram/compiler/tests/testutils.py", line 45, in local_check + self.fail("DRC failed: {}".format(a.name)) +AssertionError: DRC failed: pinv_0 + +---------------------------------------------------------------------- +Ran 1 test in 0.609s + +FAILED (failures=1) +``` + +### It didn't finish... where are my files? +* OpenRAM puts all temporary files in a temporary directory named: + * `/tmp/openram___temp` + * This allows multiple processes/users to simultaneously run + * This allows /tmp to be mapped to a RAM disk for faster performance + * After a successful run, the directory and contents are deleted + * To preserve the contents, you can run with the `-d` option for debugging +* `OPENRAM_TMP` will override the temporary directory location for debug + * `export OPENRAM_TMP="/home/myname/debugdir"` + + + +## Temporary Output Files +* DRC standard output (`*.drc.out`), errors (`*.drc.err`), and results (`*.drc.results`) +* LVS standard output (`*.lvs.out`), errors (`*.lvs.out`), and results (`*.lvs.results`) +* GDS (and Magic) files for intermediate modules (`temp.gds`, `temp.mag`) +* SPICE netlist for intermediate module results (`temp.sp`) +* Extracted layout netlist for intermediate module results (`extracted.sp`) +* Magic only: Run scripts for DRC (`run_drc.sh`) and LVS (`run_lvs.sh`) +* Calibre only: Runset file for DRC (`drc_runset`) and LVS (`lvs_runset`) + + + + diff --git a/docs/source/design_modules.md b/docs/source/design_modules.md new file mode 100644 index 00000000..f220ef2b --- /dev/null +++ b/docs/source/design_modules.md @@ -0,0 +1,152 @@ +### [Go Back](./index.md#table-of-contents) + +# Hierarchical Design Modules +This page of the documentation explains the hierarchical design modules of OpenRAM. + + + +## Table of Contents +1. [Hierarchical Design Modules](#hierarchical-design-modules-1) +1. [Bank](#bank) +1. [Port Data](#port-data) +1. [Port Address](#port-address) +1. [Plain Bitcell Array](#plain-bitcell-array) +1. [Variations of Bitcells Needed](#variations-of-bitcells-needed) +1. [Replica Bitcell Array](#replica-bitcell-array) +1. [1D Arrays](#1d-arrays) +1. [2D Arrays](#2d-arrays) +1. [Delay Line](#delay-line) +1. [Hierarchical (Address) Decoder](#hierarchical-address-decoder) + + + +## Hierarchical Design Modules +* Memory building blocks + * SRAM, Bank, Control Logic, Decoders, Column Mux, Various arrays (DFF, drivers) + * Can override every module with a custom one in the configuration file +* Each module must: + * Create netlist + * Define inputs/outputs + * Instantiate and connect sub-modules and cells + * Create layout + * Place and route itself + * Route vdd/gnd to M3 + * (Optional) Run DRC/LVS + * Analytically model timing and power + + + +## Bank + + +* Encompasses everything except + * Data and Address Flops + * Control logic + * Multi-bank logic +* Arranges ports + * Port 0 is left/bottom + * Port 1 is right/top + + + +## Port Data +* Encapsulates all of the datapath logic for a rw, w, or r port + * Sense amplifiers (read types) + * Write drivers (write types) + * Column mux (if any) + * Precharge (read or write type) (write to not destroy half selected cells in a row) +* Also includes a precharge for the replica columns + + + +## Port Address +* Encapsulates the row decoder and wordline driver for easier placement next to a bank +* Each port will have its own port\_address module + + + +## Plain Bitcell Array + + +* 2D Array of bit cells + * Each row alternately flips vertically +* Assume bitcells tile + * Boundary is determined by boundary layer in GDS + * Word line must abut + * Bit lines must abut + + + +## Variations of Bitcells Needed +* Normal bitcell for data storage +* Replica bitcell that is fixed to output a 0 value +* Dummy bitcell with bitlines disconnected (purely for wordline load and lithography regularity) + + + + + +## Replica Bitcell Array +* Bitcells: B=regular, D=dummy, R=replica +* Main bitcell array ( $\color{green}{\textrm{green}}$ ) +* Replica cols for each read port ( $\color{skyblue}{\textrm{blue}}$ ) on left or right (any number) +* Dummy bitcells on the top, bottom, left, and right for lithography regularity ( $\color{red}{\textrm{red}}$ ) +* Replica columns activate two replica bitcells + * $\color{blue}{\textrm{One}}$ driven by replica wordline + * $\color{royalblue}{\textrm{Second}}$ driven by one of the normal wordlines (dark blue) +* Second port word and bit lines not shown + * Would be on right and top + + + +## 1D Arrays + + +* Several modules have 1D arrays: + * `sense_amp_array` + * `write_driver_array` + * `precharge_array` + * `single_level_column_mux_array` + * `tri_gate_array` + * `wordline_driver` (*should change name to _array) +* `sense_amp_array`, `write_driver_array`, `tri_gate_array` match column mux stride to space out +* Wish list: Allow wide sense amplifier array to use multiple rows of sense amplifiers. + + + + + +## 2D Arrays +* Regular DFF arrays (`dff_array.py`) +* Buffered DFF arrays (`dff_buf_array.py`) +* Inverted DFF array (`dff_inv_array.py`) +* Can be $1*N$ or $N*1$ or $M*N$ + * Wish list: $M*N$ routes pins to edges + +

+ +

+ + + +## Delay Line + + +* Configurable fanout and stages + * `[4,4,4]` means 3 FO4 stages + * `[1,1,4,4]` means 2 FO1 stages followed by FO4 + + + +## Hierarchical (Address) Decoder + + +* Generic `hierarchical_predecode` class + * Places routing rails and decode inverters +* Derived to implement multiple predecoders + * `hierarchical_predecode_2x4` + * `hierarchical_predecode_3x8` + * `hierarchical_predecode_4x16` +* Hierarchical decoder uses predecoder + another decode stage +* Predecoders are also used for the column mux decode and bank select decode +* Wish list: Handle thin bitcell height diff --git a/docs/source/index.md b/docs/source/index.md new file mode 100644 index 00000000..208bc30d --- /dev/null +++ b/docs/source/index.md @@ -0,0 +1,111 @@ +# OpenRAM Documentation +![OpenRAM Logo](../../images/OpenRAM_logo_yellow_transparent.svg) + +These pages provide the documentation of OpenRAM. You can use the links below to navigate through the documentation. + + + +## Table of Contents +1. [OpenRAM Dependencies](#openram-dependencies) +1. [Supported Technologies](#supported-technologies) +1. [Basic Setup](./basic_setup.md#go-back) +1. [Basic Usage](./basic_usage.md#go-back) +1. [Bitcells](./bitcells.md#go-back) +1. [Architecture](./architecture.md#go-back) +1. [Implementation](#implementation) +1. [Technology and Tool Portability](#technology-and-tool-portability) +1. [Tutorials](./tutorials.md#go-back) +1. [Debugging and Unit Testing](./debug.md#go-back) +1. [Technology Setup](./technology_setup.md#go-back) +1. [Library Cells](./library_cells.md#go-back) +1. [Base Data Structures](./base_data_structures.md#go-back) +1. [Hierarchical Design Modules](./design_modules.md#go-back) +1. [Control Logic and Timing](./control_logic.md#go-back) +1. [Routing](./routing.md#go-back) +1. [Characterization](./characterization.md#go-back) +1. [Results](./results.md#go-back) +1. [FAQ](./FAQ.md#go-back) +1. [Contributors/Collaborators](#contributorscollaborators) + + + + +## OpenRAM Dependencies +Please see the Dockerfile for the required versions of tools. + +In general, the OpenRAM compiler has very few dependencies: ++ Docker ++ Make ++ Python 3.6 or higher ++ Various Python packages (pip install -r requirements.txt) ++ Git + +Commercial tools (optional): +* Spice Simulator + * Hspice I-2013.12-1 (or later) + * CustomSim 2017 (or later) +* DRC + * Calibre 2017.3\_29.23 +* LVS + * Calibre 2017.3\_29.23 + + + +## Supported Technologies +* NCSU FreePDK 45nm + * Non-fabricable but contains DSM rules + * Calibre or klayout for DRC/LVS +* MOSIS 0.35um (SCN4M\_SUBM) + * Fabricable technology + * Magic/Netgen or Calibre for DRC/LVS +* Skywater 130nm (sky130) + * Fabricable technology + * Magic/Netgen or klayout + + + +## Implementation +* Front-end mode + * Generates SPICE, layout views, timing models + * Netlist-only mode can skip the physical design too + * Doesn't perform DRC/LVS + * Estimates power/delay analytically +* Back-end mode + * Generates SPICE, layout views, timing models + * Performs DRC/LVS + * Can perform at each level of hierarchy or at the end + * Simulates power/delay + * Can be back-annotated or not + + + +## Technology and Tool Portability +* OpenRAM is technology independent by using a technology directory that includes: + * Technology's specific information + * Technology's rules such as DRC rules and the GDS layer map + * Custom designed library cells (6T, sense amp, DFF) to improve the SRAM density. +* For technologies that have specific design requirements, such as specialized well contacts, the user can include helper functions in the technology directory. +* Verification wrapper scripts + * Uses a wrapper interface with DRC and LVS tools that allow flexibility + * DRC and LVS can be performed at all levels of the design hierarchy to enhance bug tracking. + * DRC and LVS can be disabled completely for improved run-time or if licenses are not available. + +## Contributors/Collaborators + + +* Prof. Matthew Guthaus (UCSC) +* Prof. James Stine & Dr. Samira Ataei (Oklahoma State University) +* UCSC students: + * Bin Wu + * Hunter Nichols + * Michael Grimes + * Jennifer Sowash + * Jesse Cirimelli-Low + +* Many other past students: + * Jeff Butera + * Tom Golubev + * Marcelo Sero + * Seokjoong Kim + + diff --git a/docs/source/library_cells.md b/docs/source/library_cells.md new file mode 100644 index 00000000..732e9667 --- /dev/null +++ b/docs/source/library_cells.md @@ -0,0 +1,96 @@ +### [Go Back](./index.md#table-of-contents) + +# Library Cells +This page of the documentation explains the library cells of OpenRAM. + + + +## Table of Contents +1. [Required Hard/Custom Cells](#required-hardcustom-cells) +1. [Bitcell(s)](#bitcells) +1. [Multiport Bitcells](#multiport-bitcells) +1. [Parameterized Bitcell](#parameterized-bitcell) +1. [Sense Amplifier](#sense-amplifier) +1. [DFF](#dff) +1. [Tristate/Write Driver](#tristatewrite-driver) + + + +## Required Hard/Custom Cells +* Located in + * `$OPENRAM_TECH//gds_lib` + * `$OPENRAM_TECH//sp_lib` +* A few library cells with layout and SPICE: + * Bitcell (and dummy and replica bitcell) + * Sense amplifier + * DFF (from a standard cell library) + * (Removing soon: write driver, tristate) +* P&R border layer defined for placement +* Sense amplifier pitch matched width to bitcell + + + +## Bitcell(s) +* Python code is in `$OPENRAM_HOME/bitcells` + * Layout in `$OPENRAM_TECH//gds_lib ` + * SPICE in `$OPENRAM_TECH//sp_lib` +* Can be a foundry bitcell if you have the GDS and SPICE. +* May include multiple port configurations: + * `bitcell.py` uses `cell_6t.{gds,sp}` - standard 1rw port + * `bitcell_1w_1r.py` uses `cell_1w_1r.{gds,sp}` for 1w and 1r port + * `bitcell_1rw_1r.py` uses `cell_1rw_1r.{gds,sp}` for 1rw and 1r port +* Wish list: pin names are fixed right now as `bl`, `br`, `wl`, `vdd`, `gnd` + + + +## Multiport Bitcells +* Based on 6T SRAM cell + * Standard read-write + * Isolated read-only ports + * Write-only port (not sized for reads) +* Can accommodate foundry bitcells + +![Multiport Bitcells](../assets/images/bitcells/multiport_bitcells.png) + + + +## Parameterized Bitcell +* If a custom bitcell is not available, we create one with user design rules. + * Not good for area, but may still be better than DFFs. + * Can be useful for simulation/functional work before custom bitcell is available. + * Example 1 RW pbitcell compared to custom 1RW + + + + + + +## Sense Amplifier +* Needs a sense amplifier that is pitch matched to the bitcell. + * `$OPENRAM_TECH/gds_lib/sense_amp.gds` + * `$OPENRAM_TECH/sp_lib/sense_amp.sp` + * `$OPENRAM_HOME/modules/sense_amp.py` +* Wish list: pin names are fixed right now as `bl`, `br`, `dout`, `en`, `vdd`, `gnd` + + + +## DFF +* Needs a standard cell DFF for the address and data registers. + * `$OPENRAM_TECH/gds_lib/dff.gds ` + * `$OPENRAM_TECH/sp_lib/dff.sp` + * `$OPENRAM_HOME/modules/dff.py` +* Have auxiliary code to create: + * Buffered DFFs (`dff_buf.py`) using dynamically generated inverters (pinv) + * Inverted output DFFs (`dff_inv.py`) using a dynamically generated inverters (pinv) + * 2-D DFF arrays + * Regular DFF arrays (`dff_array.py`) + * Buffered DFF arrays (`dff_buf_array.py`) + * Inverted DFF array (`dff_inv_array.py`) +* Wish list: pin names are fixed right now as `D`, `Q`, `Qb`, `clk`, `vdd`, `gnd` + + + +## Tristate/Write Driver +* Tristate is used for multi-bank implementations +* Write driver drives the data onto the bitlines +* Both of these are currently library cells, but plans are to make them dynamically generated (`ptristate.py` and `pwrite_driver.py`) diff --git a/docs/source/results.md b/docs/source/results.md new file mode 100644 index 00000000..8909049c --- /dev/null +++ b/docs/source/results.md @@ -0,0 +1,67 @@ +### [Go Back](./index.md#table-of-contents) + +# Results +This page of the documentation explains the results of OpenRAM. + + + +## Table of Contents +1. [Small Layouts](#small-layouts) +1. [Relative Planar Bitcells](#relative-planar-bitcells-035um-scmos) +1. [SRAM Area](#sram-area) +1. [Generated Layout by OpenRAM](#generated-layout-by-openram-for-a-multiport-6r2w-sram-in-32-nm-soi-cmos-technology) +1. [Timing and Density Results for Generated SRAMs](#timing-and-density-results-for-generated-srams) +1. [Comparison with Fabricated SRAMs](#comparison-with-fabricated-srams) +1. [Conclusions](#conclusions) + + + +## Small Layouts +| | | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| 512 x 16b x 1rw FreePDK45 | 2048 x 32b x 1rw FreePDK45 | + + + +## Relative Planar Bitcells (0.35um SCMOS) +| | | | +| :-----------------------------------------------: | :------------------------------------------------: | :--------------------------------------------------: | +| Standard 6T (1rw) 6.8um x 9.2um | Isolated Read 10T (1rw, 1r) 10.9um x 13.9um | DFF 21.9um x 21.2um (from OSU standard cell library) | + + + +## SRAM Area +![SRAM Area](../assets/images/results/sram_area.png) + + + +## Generated Layout by OpenRAM for a multiport (6R/2W) SRAM in 32 nm SOI CMOS Technology +![Generated Layout](../assets/images/results/generated_layout.jpg) + + + +## Timing and Density Results for Generated SRAMs +![Timing and Density Results](../assets/images/results/timing_and_density_results.png) + + + +## Comparison with Fabricated SRAMs +| $\textrm{Reference}$ | $\textrm{Feature Size}$ | $\textrm{Technology}$ | $\textrm{Density } (Mb/mm^2)$ | +| :---------------------- | :---------------------: | :-------------------: | :---------------------------: | +| $\textrm{IEEE-VLSI'08}$ | $65 nm$ | $\textrm{CMOS}$ | $0.7700$ | +| $\textrm{JSSC'11}$ | $45 nm$ | $\textrm{CMOS}$ | $0.3300$ | +| $\textrm{JSSC'13}$ | $40 nm$ | $\textrm{CMOS}$ | $0.9400$ | +| $\textrm{OpenRAM}$ | $45 nm$ | $\textrm{FreePDK45}$ | $0.8260$ | +| $\textrm{JSSC'92}$ | $0.5 \mu m$ | $\textrm{CMOS}$ | $0.0036$ | +| $\textrm{JSSC'94}$ | $0.5 \mu m$ | $\textrm{BICMOS}$ | $0.0020$ | +| $\textrm{JSSC'99}$ | $0.5 \mu m$ | $\textrm{CMOS}$ | $0.0050$ | +| $\textrm{OpenRAM}$ | $0.5 \mu m$ | $\textrm{SCMOS}$ | $0.0050$ | + + + +## Conclusions +* The main motivation behind OpenRAM is to promote and simplify memory-related research in academia and provides a platform to implement and test new memory designs. +* OpenRAM is open-sourced, flexible, and portable and can be adapted to various technologies. +* OpenRAM generates the circuit, functional model, and layout of variable-sized SRAMs. +* OpenRAM provides a memory characterizer for synthesis timing/power models. +* We are also actively introducing new features, such as non-6T memories, variability characterization, word-line segmenting, characterization speed-up, etc. diff --git a/docs/source/routing.md b/docs/source/routing.md new file mode 100644 index 00000000..bcaa45fa --- /dev/null +++ b/docs/source/routing.md @@ -0,0 +1,56 @@ +### [Go Back](./index.md#table-of-contents) + +# Routing +This page of the documentation explains the routing of OpenRAM. + + + +## Table of Contents +1. [Power Supply Options](#power-supply-options) +1. [Power Routing](#power-routing) +1. [Power Supply Algorithm](#power-supply-algorithm) +1. [Channel Router](#channel-router) + + + +## Power Supply Options +* Unrouted + * Leave must-connect metal 3 pins for vdd and gnd within the array +* Grid + * Connect in a metal 3 and 4 grid + * Blockage aware + * Can encounter DRC errors with off-grid pins + * Works with commercial tools but not so well with OpenRoad +* Work in Progress: Hanan Grid / Steiner Tree: + * Route tree on Hanan metal 3 and 4 grid instead of full grid + * Blockage aware + + + +## Power Routing + + +* All power pins are brought to M3 and routed as a grid on M3/M4 +* Considers blockages of M3/M4 by control and data signals +* Considers wide/long metal spacing rules + + + +## Power Supply Algorithm +* 1st: Route vertical and horizontal grids (blockage aware, allow connection to correct supply) +* 2nd: Check direct overlaps of power pins +* 3rd: Single direction probes to connect +* 4th: A* maze router + + + +## Channel Router +* SRAMs typically try to use minimal layers of metal + * Primarily used to connect decoders, input/output circuitry, or control logic +* Wish list + * Minimize number of tracks + * Must consider impact on floorplan + +| | | +| :-------------------------------------------------------------------------: | :---------------------------------------------------------------------: | +| Credit: Chen & Chang, EDA Handbook, Chapter 12, Global and detailed routing | Sense amp to data flop connection | diff --git a/docs/source/technology_setup.md b/docs/source/technology_setup.md new file mode 100644 index 00000000..1d0c9d98 --- /dev/null +++ b/docs/source/technology_setup.md @@ -0,0 +1,125 @@ +### [Go Back](./index.md#table-of-contents) + +# Technology Setup +This page of the documentation explains the technology setup of OpenRAM. + + + +## Table of Contents +1. [Technology Directories](#technology-directories) +1. Technology Configuration: + 1. [Layer Map](#technology-configuration-layer-map) + 1. [GDS](#technology-configuration-gds) + 1. [DRC](#technology-configuration-drc) + 1. [SPICE](#technology-configuration-spice) + 1. [Parameters](#technology-configuration-parameters) + + + +## Technology Directories +* Environment variable OPENRAM\_TECH specifies list of technology directories + * Similar to `*nix $PATH` +* Directory structure: + ``` + techname/ + __init__.py -- Sets up PDK environment + tech/ -- Contains technology configuration + __init__.py -- Loads all modules + tech.py -- SPICE, DRC, GDS, and layer config + gds_lib/ -- Contains .gds files for each lib cell + sp_lib/ -- Contains .sp file for each lib cell + models/ -- Contains SPICE device corner models + (tf/) -- May contain some PDK material + (mag_lib/) -- May contain other layout formats + ``` + + + +## Technology Configuration: Layer Map +* Layer map contains mapping of layer names to GDS layers +* Layer names are used in OpenRAM code directly + ```python + layer={} + layer["vtg"] = -1 + layer["vth"] = -1 + layer["contact"] = 47 + layer["pwell"] = 41 + ... + layer["metal4"] = 31 + layer["text"] = 63 + layer["boundary"] = 63 + layer["blockage"] = 83 + ``` + + + +## Technology Configuration: GDS +* OpenRAM uses the gdsMill library (included and heavily modified) +* Units defined for GDS format + * First number is DB units per user units + * Second number is DB unit in meters + ```python + # GDS file info + GDS={} + # gds units + GDS["unit"]=(0.001,1e-6) + # default label zoom + GDS["zoom"] = 0.5 + ``` +* Zoom defines default zoom for labels +* More info on the GDS format at: + * http://boolean.klaasholwerda.nl/interface/bnf/gdsformat.html + + + +## Technology Configuration: DRC +* Creates the design\_rule class with several parts: + * Grid size + * Location of DRC, LVS, PEX rules and layer map + * Subset of design rules for FEOL and BEOL +* Design rules have common naming scheme (names used in OpenRAM) + * `minwidth_` + * `_to_` + * `_extend_` + * `minarea_` + * Allows rule tables for complex rules +```python +# Minimum spacing of metal3 wider than 0.09 & longer than 0.3 = 0.09 +# Minimum spacing of metal3 wider than 0.27 & longer than 0.9 = 0.27 +# Minimum spacing of metal3 wider than 0.5 & longer than 1.8 = 0.5 +# Minimum spacing of metal3 wider than 0.9 & longer than 2.7 = 0.9 +# Minimum spacing of metal3 wider than 1.5 & longer than 4.0 = 1.5 +drc["metal3_to_metal3"] = drc_lut({(0.00, 0.0) : 0.07, + (0.09, 0.3) : 0.09, + (0.27, 0.9) : 0.27, + (0.50, 1.8) : 0.5, + (0.90, 2.7) : 0.9, + (1.50, 4.0) : 1.5}) +``` + + + +## Technology Configuration: SPICE +* Device models (and corners) +* Defaults simulation values + * Voltage + * Temperature + * Feasible period for simulation + * Rise/fall input slews +* Analytical parameters + * For example, device capacitance and "on" resistance + * Used for analytical delay and power estimation + + + +## Technology Configuration: Parameters +* Default design parameters + * Being cleaned up and standardized... +* Defaults simulation values + * Voltage + * Temperature + * Feasible period for simulation + * Rise/fall input slews +* Analytical parameters + * Used for analytical delay and power estimation + * E.g. device capacitance and "on" resistance diff --git a/docs/source/tutorials.md b/docs/source/tutorials.md new file mode 100644 index 00000000..c6f22dd6 --- /dev/null +++ b/docs/source/tutorials.md @@ -0,0 +1,10 @@ +### [Go Back](./index.md#table-of-contents) + +# Tutorials +This page of the documentation includes tutorials for OpenRAM. + + + +## Table of Contents +1. []() + \ No newline at end of file diff --git a/macros/Makefile b/macros/Makefile index 630541c0..a61a180e 100644 --- a/macros/Makefile +++ b/macros/Makefile @@ -65,7 +65,7 @@ OPENRAM_TMP=/openram/macros/$*/tmp %.ok: configs/%.py @echo "Building $*" @mkdir -p $* - @$(DOCKER_CMD) python3 -u /openram/compiler/openram.py $(OPENRAM_OPTS) -o $* -p /openram/macros/$* /openram/macros/$< && touch $@ + @$(DOCKER_CMD) python3 -u /openram/sram_compiler.py $(OPENRAM_OPTS) -o $* -p /openram/macros/$* /openram/macros/$< && touch $@ .DELETE_ON_ERROR: $(STAMPS) diff --git a/openram.mk b/openram.mk index f169fa32..9c131580 100644 --- a/openram.mk +++ b/openram.mk @@ -1,6 +1,6 @@ OPENRAM_HOME := $(abspath $(TOP_DIR)/compiler) OPENRAM_TECH := $(abspath $(TOP_DIR)/technology) -OPENRAM_COMPILER := $(OPENRAM_HOME)/openram.py +OPENRAM_COMPILER := $(abspath $(TOP_DIR)/sram_compiler.py) PDK_ROOT ?= $(TOP_DIR) diff --git a/pyproject.toml b/pyproject.toml new file mode 100644 index 00000000..5aebe600 --- /dev/null +++ b/pyproject.toml @@ -0,0 +1,15 @@ +[build-system] +requires = ["setuptools"] +build-backend = "setuptools.build_meta" + +[project] +name = "openram" +version = "1.2.0" +description = "An open-source static random access memory (SRAM) compiler" +authors = [ + { name="Matthew Guthaus", email="mrg@ucsc.edu" }, +] +keywords = [ "sram", "magic", "gds", "netgen", "ngspice", "netlist" ] +readme = "README.md" +license = { text = "BSD-3-Clause License" } +requires-python = ">=3.6" \ No newline at end of file diff --git a/setup.py b/setup.py new file mode 100644 index 00000000..302e91e2 --- /dev/null +++ b/setup.py @@ -0,0 +1,57 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +from setuptools import setup, find_namespace_packages + + +# Include these folder from the root of repo as submodules +include = ["compiler", "docker", "technology", "macros"] +# Exclude files/folders with these words +exclude = ["docs", "images"] + + +# Find all modules inside the 'compiler' folder +dirs = [] +for dir in find_namespace_packages(): + if any(x in dir for x in exclude): + continue + dirs.append(dir) + +# Replace 'compiler' with 'openram' for package names +packages = [] +for dir in dirs: + packages.append(dir) + +# Make the included folders submodules of openram package +for i in range(len(packages)): + if any(x in packages[i] for x in include): + packages[i] = "openram." + packages[i] + +# Fix directory paths +for i in range(len(dirs)): + dirs[i] = dirs[i].replace(".", "/") + +# Insert the root as the openram module +packages.insert(0, "openram") +dirs.insert(0, "") + +# Zip package names and their paths +package_dir = {k: v for k, v in zip(packages, dirs)} + + +# Create a list of required packages +with open("requirements.txt") as f: + reqs = f.read().splitlines() + + +# Call the setup to create the package +setup( + packages=packages, + package_dir=package_dir, + include_package_data=True, + install_requires=reqs, +) diff --git a/compiler/openram.py b/sram_compiler.py similarity index 56% rename from compiler/openram.py rename to sram_compiler.py index fbbf4466..1dc3812c 100755 --- a/compiler/openram.py +++ b/sram_compiler.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -17,48 +17,51 @@ a Liberty (.lib) file for timing analysis/optimization """ import sys +import os import datetime -import globals as g +try: + import openram +except: + # If openram library isn't found as a python package, + # import it from the $OPENRAM_HOME path. + import importlib.util + OPENRAM_HOME = os.getenv("OPENRAM_HOME") + # Import using spec since the directory can be named something + # other than "openram". + spec = importlib.util.spec_from_file_location("openram", "{}/../__init__.py".format(OPENRAM_HOME)) + module = importlib.util.module_from_spec(spec) + sys.modules["openram"] = module + spec.loader.exec_module(module) + import openram -(OPTS, args) = g.parse_args() +(OPTS, args) = openram.parse_args() # Check that we are left with a single configuration file as argument. if len(args) != 1: - print(g.USAGE) + print(openram.USAGE) sys.exit(2) # These depend on arguments, so don't load them until now. -import debug +from openram import debug # Parse config file and set up all the options -g.init_openram(config_file=args[0], is_unit_test=False) +openram.init_openram(config_file=args[0]) # Ensure that the right bitcell exists or use the parameterised one -g.setup_bitcell() +openram.setup_bitcell() # Only print banner here so it's not in unit tests -g.print_banner() +openram.print_banner() # Keep track of running stats start_time = datetime.datetime.now() -g.print_time("Start", start_time) +openram.print_time("Start", start_time) # Output info about this run -g.report_status() +openram.report_status() -from modules import sram_config - - -# Configure the SRAM organization -c = sram_config(word_size=OPTS.word_size, - num_words=OPTS.num_words, - write_size=OPTS.write_size, - num_banks=OPTS.num_banks, - words_per_row=OPTS.words_per_row, - num_spare_rows=OPTS.num_spare_rows, - num_spare_cols=OPTS.num_spare_cols) -debug.print_raw("Words per row: {}".format(c.words_per_row)) +debug.print_raw("Words per row: {}".format(OPTS.words_per_row)) output_extensions = ["lvs", "sp", "v", "lib", "py", "html", "log"] # Only output lef/gds if back-end @@ -72,16 +75,14 @@ debug.print_raw("Output files are: ") for path in output_files: debug.print_raw(path) - -from modules import sram -s = sram(name=OPTS.output_name, - sram_config=c) +# Create an SRAM (we can also pass sram_config, see documentation/tutorials for details) +from openram import sram +s = sram() # Output the files for the resulting SRAM s.save() # Delete temp files etc. -g.end_openram() -g.print_time("End", datetime.datetime.now(), start_time) - +openram.end_openram() +openram.print_time("End", datetime.datetime.now(), start_time) diff --git a/technology/freepdk45/__init__.py b/technology/freepdk45/__init__.py index 6d9e759d..615cf966 100644 --- a/technology/freepdk45/__init__.py +++ b/technology/freepdk45/__init__.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. @@ -13,7 +13,7 @@ the trunk import sys import os -import debug +from openram import debug TECHNOLOGY = "freepdk45" diff --git a/technology/freepdk45/tech/__init__.py b/technology/freepdk45/tech/__init__.py index 752537ad..36ea53b8 100644 --- a/technology/freepdk45/tech/__init__.py +++ b/technology/freepdk45/tech/__init__.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 76522ff3..bcab29d3 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import os -import drc as d +from openram import drc as d #from drc.design_rules import design_rules #from drc.module_type import module_type #from drc.custom_cell_properties import cell_properties diff --git a/technology/scn3me_subm/__init__.py b/technology/scn3me_subm/__init__.py index 66af34fe..4d45664c 100644 --- a/technology/scn3me_subm/__init__.py +++ b/technology/scn3me_subm/__init__.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -#Copyright (c) 2016-2021 Regents of the University of California and The Board +#Copyright (c) 2016-2022 Regents of the University of California and The Board #of Regents for the Oklahoma Agricultural and Mechanical College #(acting for and on behalf of Oklahoma State University) #All rights reserved. diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 39ca0cfc..6e8b599f 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -1,7 +1,7 @@ import os -from design_rules import * -from module_type import * -from custom_cell_properties import CellProperties +from openram.drc.design_rules import * +from openram.drc.module_type import * +from openram.drc.custom_cell_properties import CellProperties """ File containing the process technology parameters for SCMOS 3me, subm, 180nm. @@ -306,4 +306,4 @@ pex_name = "magic" ##END Technology Tool Preferences ################################################### array_row_multiple = 1 -array_col_multiple = 1 \ No newline at end of file +array_col_multiple = 1 diff --git a/technology/scn4m_subm/__init__.py b/technology/scn4m_subm/__init__.py index 1a17c4da..a5b5543a 100644 --- a/technology/scn4m_subm/__init__.py +++ b/technology/scn4m_subm/__init__.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/technology/scn4m_subm/tech/.magicrc b/technology/scn4m_subm/tech/.magicrc index 8fdad1b7..29c9977f 100644 --- a/technology/scn4m_subm/tech/.magicrc +++ b/technology/scn4m_subm/tech/.magicrc @@ -1,3 +1,12 @@ +# Check if the openram package is installed. If so, append that path to $OPENRAM_TECH. +# If $OPENRAM_TECH isn't defined and the package is installed, use the package directory. +set openramhome [exec echo -e "import os\ntry:\n import openram\n print(os.path.dirname(openram.__file__))\nexcept:\n print(\"notinstalled\")" | python3 -] +set openramtech "${openramhome}/technology/scn4m_subm/tech" +if { [info exists ::env(OPENRAM_TECH)] && ($openramhome != "notinstalled") } { + set ::env(OPENRAM_TECH) $env(OPENRAM_TECH):$openramtech +} elseif { $openramhome != "notinstalled" } { + set ::env(OPENRAM_TECH) $openramtech +} set openram_paths [split $::env(OPENRAM_TECH) ":"] foreach p $openram_paths { path sys +$p/scn4m_subm/tech diff --git a/technology/scn4m_subm/tech/__init__.py b/technology/scn4m_subm/tech/__init__.py index 752537ad..36ea53b8 100644 --- a/technology/scn4m_subm/tech/__init__.py +++ b/technology/scn4m_subm/tech/__init__.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index e940ce29..b6f3683a 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -1,12 +1,12 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2022 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. # import os -import drc as d +from openram import drc as d #from drc.design_rules import design_rules #from drc.module_type import module_type #from drc.custom_cell_properties import cell_properties diff --git a/technology/sky130/__init__.py b/technology/sky130/__init__.py index 409f0032..90b8f84a 100644 --- a/technology/sky130/__init__.py +++ b/technology/sky130/__init__.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # diff --git a/technology/sky130/custom/sky130_bitcell.py b/technology/sky130/custom/sky130_bitcell.py index 908ff45d..26216932 100644 --- a/technology/sky130/custom/sky130_bitcell.py +++ b/technology/sky130/custom/sky130_bitcell.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from tech import cell_properties as props -from modules import bitcell_base +from openram import debug +from openram.modules import bitcell_base +from openram.tech import cell_properties as props class sky130_bitcell(bitcell_base): diff --git a/technology/sky130/custom/sky130_bitcell_array.py b/technology/sky130/custom/sky130_bitcell_array.py index 2c7f5cd5..e0945449 100644 --- a/technology/sky130/custom/sky130_bitcell_array.py +++ b/technology/sky130/custom/sky130_bitcell_array.py @@ -1,15 +1,15 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from modules import bitcell_array +from openram import debug +from openram.modules import bitcell_array +from openram.sram_factory import factory +from openram import OPTS from .sky130_bitcell_base_array import sky130_bitcell_base_array -from globals import OPTS -from sram_factory import factory class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): @@ -29,10 +29,10 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): # This will create a default set of bitline/wordline names self.create_all_bitline_names() self.create_all_wordline_names() - self.create_netlist() if not OPTS.netlist_only: self.create_layout() + self.add_supply_pins() def add_modules(self): """ Add the modules used in this design """ diff --git a/technology/sky130/custom/sky130_bitcell_base_array.py b/technology/sky130/custom/sky130_bitcell_base_array.py index 1604fa02..f490f05a 100644 --- a/technology/sky130/custom/sky130_bitcell_base_array.py +++ b/technology/sky130/custom/sky130_bitcell_base_array.py @@ -1,16 +1,16 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from base import geometry -from sram_factory import factory -from modules import bitcell_base_array -from globals import OPTS -from tech import layer +from openram import debug +from openram.base import geometry +from openram.modules import bitcell_base_array +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS class sky130_bitcell_base_array(bitcell_base_array): @@ -125,11 +125,23 @@ class sky130_bitcell_base_array(bitcell_base_array): def add_supply_pins(self): """ Add the layout pins """ # Copy a vdd/gnd layout pin from every cell + + for inst in self.insts: + if "wlstrap" in inst.name: + try: + self.copy_layout_pin(inst, "VPWR", "vdd") + except: + pass + try: + self.copy_layout_pin(inst, "VGND", "gnd") + except: + pass for row in range(self.row_size): for col in range(self.column_size): inst = self.cell_inst[row, col] for pin_name in ["vdd", "gnd"]: self.copy_layout_pin(inst, pin_name) + if row == 2: #add only 1 label per col if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins: @@ -142,7 +154,7 @@ class sky130_bitcell_base_array(bitcell_base_array): if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins: try: - from tech import layer_override + from openram.tech import layer_override if layer_override['VNB']: pin = inst.get_pin("vnb") self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center())) diff --git a/technology/sky130/custom/sky130_col_cap.py b/technology/sky130/custom/sky130_col_cap.py index eb2383e5..8912b0f5 100644 --- a/technology/sky130/custom/sky130_col_cap.py +++ b/technology/sky130/custom/sky130_col_cap.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from base import design -from tech import cell_properties as props +from openram import debug +from openram.base import design +from openram.tech import cell_properties as props class sky130_col_cap(design): diff --git a/technology/sky130/custom/sky130_col_cap_array.py b/technology/sky130/custom/sky130_col_cap_array.py index 940296d3..3c50856a 100644 --- a/technology/sky130/custom/sky130_col_cap_array.py +++ b/technology/sky130/custom/sky130_col_cap_array.py @@ -1,15 +1,15 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -from sram_factory import factory +from openram.base import geometry +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS from .sky130_bitcell_base_array import sky130_bitcell_base_array -from globals import OPTS -from base import geometry -from tech import layer class sky130_col_cap_array(sky130_bitcell_base_array): """ @@ -230,7 +230,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array): if 'VNB' or 'vnb' in self.cell_inst[col].mod.pins: try: - from tech import layer_override + from openram.tech import layer_override if layer_override['VNB']: pin = inst.get_pin("vnb") self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center())) diff --git a/technology/sky130/custom/sky130_corner.py b/technology/sky130/custom/sky130_corner.py index 858a0a4a..8190cb27 100644 --- a/technology/sky130/custom/sky130_corner.py +++ b/technology/sky130/custom/sky130_corner.py @@ -1,14 +1,14 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from base import design -from base import get_libcell_size -from tech import layer, GDS +from openram import debug +from openram.base import design +from openram.base import get_libcell_size +from openram.tech import layer, GDS class sky130_corner(design): diff --git a/technology/sky130/custom/sky130_dummy_array.py b/technology/sky130/custom/sky130_dummy_array.py index bfdca620..ce5f93b4 100644 --- a/technology/sky130/custom/sky130_dummy_array.py +++ b/technology/sky130/custom/sky130_dummy_array.py @@ -1,15 +1,15 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # +from openram.base import geometry +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS from .sky130_bitcell_base_array import sky130_bitcell_base_array -from sram_factory import factory -from globals import OPTS -from base import geometry -from tech import layer class sky130_dummy_array(sky130_bitcell_base_array): """ @@ -177,7 +177,7 @@ class sky130_dummy_array(sky130_bitcell_base_array): if 'VNB' or 'vnb' in self.cell_inst[row, col].mod.pins: try: - from tech import layer_override + from openram.tech import layer_override if layer_override['VNB']: pin = inst.get_pin("vnb") self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center())) diff --git a/technology/sky130/custom/sky130_dummy_bitcell.py b/technology/sky130/custom/sky130_dummy_bitcell.py index 58ef8026..e36d40e6 100644 --- a/technology/sky130/custom/sky130_dummy_bitcell.py +++ b/technology/sky130/custom/sky130_dummy_bitcell.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from tech import cell_properties as props -from modules import bitcell_base +from openram import debug +from openram.modules import bitcell_base +from openram.tech import cell_properties as props class sky130_dummy_bitcell(bitcell_base): diff --git a/technology/sky130/custom/sky130_internal.py b/technology/sky130/custom/sky130_internal.py index 10637384..cba59b98 100644 --- a/technology/sky130/custom/sky130_internal.py +++ b/technology/sky130/custom/sky130_internal.py @@ -1,33 +1,40 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from base import design -from base import get_libcell_size -from tech import layer, GDS +from copy import deepcopy +from openram.modules import internal_base +from openram.tech import cell_properties as props - -class sky130_internal(design): +class sky130_internal(internal_base): def __init__(self, version, name=""): - super().__init__(name) - + prop = deepcopy(props.internal) + prop.boundary_layer = "mem" if version == "wlstrap": self.name = "sky130_fd_bd_sram__sram_sp_wlstrap" + prop.port_order = ["vdd"] + prop.port_types = ["POWER"] + prop.port_map = {'vdd': 'VPWR'} elif version == "wlstrap_p": self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p" + prop.port_order = ["gnd"] + prop.port_types = ["GROUND"] + prop.port_map = {'gnd': 'VGND'} elif version == "wlstrapa": self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa" + prop.port_order = ["vdd"] + prop.port_types = ["POWER"] + prop.port_map = {'vdd': 'VPWR'} elif version == "wlstrapa_p": self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p" + prop.port_order = ["gnd"] + prop.port_types = ["GROUND"] + prop.port_map = {'gnd': 'VGND'} else: debug.error("Invalid version", -1) - design.__init__(self, name=self.name) - (self.width, self.height) = get_libcell_size(self.name, - GDS["unit"], - layer["mem"]) - # pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"]) + + super().__init__(name, cell_name=self.name, prop=prop) diff --git a/technology/sky130/custom/sky130_replica_bitcell.py b/technology/sky130/custom/sky130_replica_bitcell.py index 2b30fb7a..9fef4d5a 100644 --- a/technology/sky130/custom/sky130_replica_bitcell.py +++ b/technology/sky130/custom/sky130_replica_bitcell.py @@ -1,15 +1,15 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from modules import bitcell_base -from base import logical_effort -from tech import parameter, drc -from tech import cell_properties as props +from openram import debug +from openram.base import logical_effort +from openram.modules import bitcell_base +from openram.tech import parameter, drc +from openram.tech import cell_properties as props class sky130_replica_bitcell(bitcell_base): @@ -43,7 +43,7 @@ class sky130_replica_bitcell(bitcell_base): def analytical_power(self, corner, load): """Bitcell power in nW. Only characterizes leakage.""" - from tech import spice + from openram.tech import spice leakage = spice["bitcell_leakage"] dynamic = 0 # temporary total_power = self.return_power(dynamic, leakage) diff --git a/technology/sky130/custom/sky130_replica_bitcell_array.py b/technology/sky130/custom/sky130_replica_bitcell_array.py index c7b3c609..396a2c73 100644 --- a/technology/sky130/custom/sky130_replica_bitcell_array.py +++ b/technology/sky130/custom/sky130_replica_bitcell_array.py @@ -1,20 +1,20 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from modules import replica_bitcell_array -from base import vector -from .sky130_bitcell_base_array import sky130_bitcell_base_array -from base import round_to_grid from math import sqrt -from tech import drc -from tech import array_row_multiple -from tech import array_col_multiple -from globals import OPTS +from openram import debug +from openram.base import vector +from openram.base import round_to_grid +from openram.modules import replica_bitcell_array +from openram.tech import drc +from openram.tech import array_row_multiple +from openram.tech import array_col_multiple +from openram import OPTS +from .sky130_bitcell_base_array import sky130_bitcell_base_array class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_array): @@ -228,10 +228,6 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar self.add_via_stack_center(from_layer=pin.layer, to_layer='m2', offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0)) - #self.add_power_pin(name=pin_name, - # loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0), - # start_layer=pin.layer, - # end_layer='m2') # add well contacts to perimeter cells @@ -277,9 +273,6 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar self.add_via_stack_center(from_layer=pin.layer, to_layer='m2', offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0)) - #self.add_power_pin(name=pin_name, - # loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0), - # start_layer=pin.layer) min_area = drc["minarea_{}".format('m3')] for track,supply, offset in zip(range(1,5),['vdd','vdd','gnd','gnd'],[min_area * 6,min_area * 6, 0, 0]): diff --git a/technology/sky130/custom/sky130_replica_column.py b/technology/sky130/custom/sky130_replica_column.py index 0425160d..d6fecd56 100644 --- a/technology/sky130/custom/sky130_replica_column.py +++ b/technology/sky130/custom/sky130_replica_column.py @@ -1,16 +1,16 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug +from openram import debug +from openram.base import geometry +from openram.sram_factory import factory +from openram.tech import layer +from openram import OPTS from .sky130_bitcell_base_array import sky130_bitcell_base_array -from sram_factory import factory -from globals import OPTS -from base import geometry -from tech import layer class sky130_replica_column(sky130_bitcell_base_array): @@ -90,8 +90,8 @@ class sky130_replica_column(sky130_bitcell_base_array): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - #self.add_pin("top_gate", "INPUT") - #self.add_pin("bot_gate", "INPUT") + self.add_pin("top_gate", "INPUT") + self.add_pin("bot_gate", "INPUT") def add_modules(self): self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1") @@ -246,7 +246,7 @@ class sky130_replica_column(sky130_bitcell_base_array): if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins: try: - from tech import layer_override + from openram.tech import layer_override if layer_override['VNB']: pin = inst.get_pin("vnb") self.add_label("gnd", pin.layer, pin.center()) diff --git a/technology/sky130/custom/sky130_row_cap.py b/technology/sky130/custom/sky130_row_cap.py index 1c81b8dd..19da1570 100644 --- a/technology/sky130/custom/sky130_row_cap.py +++ b/technology/sky130/custom/sky130_row_cap.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -import debug -from base import design -from tech import cell_properties as props +from openram import debug +from openram.base import design +from openram.tech import cell_properties as props class sky130_row_cap(design): diff --git a/technology/sky130/custom/sky130_row_cap_array.py b/technology/sky130/custom/sky130_row_cap_array.py index 45b63c77..70d5f91d 100644 --- a/technology/sky130/custom/sky130_row_cap_array.py +++ b/technology/sky130/custom/sky130_row_cap_array.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # -from sram_factory import factory +from openram.sram_factory import factory +from openram import OPTS from .sky130_bitcell_base_array import sky130_bitcell_base_array -from globals import OPTS class sky130_row_cap_array(sky130_bitcell_base_array): diff --git a/technology/sky130/tech/__init__.py b/technology/sky130/tech/__init__.py index 680b0b9c..c6bd5798 100644 --- a/technology/sky130/tech/__init__.py +++ b/technology/sky130/tech/__init__.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py old mode 100644 new mode 100755 index 6957530b..b0e4a07a --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -1,13 +1,13 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California # All rights reserved. # import os -import drc as d +from openram import drc as d """ File containing the process technology parameters for Skywater 130nm. @@ -782,14 +782,26 @@ library_prefix_name = "sky130_fd_bd_sram__" # This will look for a maglef file and copy it over the mag file # before DRC after extraction +# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell +# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce +# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell +# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce +# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell +# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell +# gds flatglob sky130_fd_bd_sram__sram_sp_cell_fom_serifs + flatglob = ["*_?mos_m*", "sky130_fd_bd_sram__sram_sp_cell_fom_serifs", - "sky130_fd_bd_sram__openram_sp_cell_opt1a_cell", - "sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce", + + "sky130_fd_bd_sram__sram_sp_cell", "sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell", + "sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_cell", + + "sky130_fd_bd_sram__sram_sp_cell_opt1_ce", "sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce", - "sky130_fd_bd_sram__openram_sp_cell_opt1a_cell", - "sky130_fd_bd_sram__sram_sp_cell_fom_serifs"] + "sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce", + "sky130_fd_bd_sram__sram_sp_wlstrap_ce", + "sky130_fd_bd_sram__sram_sp_wlstrap_p_ce"] blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell", "sky130_fd_bd_sram__openram_dp_cell_dummy",