mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 01:24:39 +02:00
Move sram and sram_config to openram namespace
This commit is contained in:
Eren Dogan
@@ -83,6 +83,4 @@ from .write_driver_array import *
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from .write_driver import *
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from .write_mask_and_array import *
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from .sram_1bank import *
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from .sram_config import *
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from .sram import *
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from .internal_base import *
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@@ -1,194 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import os
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import shutil
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import datetime
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from openram import debug
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from openram.characterizer import functional
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from openram.modules import sram_config as config
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from openram import OPTS, print_time
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class sram():
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"""
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This is not a design module, but contains an SRAM design instance.
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It could later try options of number of banks and organization to compare
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results.
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We can later add visualizer and other high-level functions as needed.
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"""
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def __init__(self, sram_config=None, name=None):
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# Create default configs if custom config isn't provided
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if sram_config is None:
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sram_config = config(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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write_size=OPTS.write_size,
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num_banks=OPTS.num_banks,
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words_per_row=OPTS.words_per_row,
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num_spare_rows=OPTS.num_spare_rows,
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num_spare_cols=OPTS.num_spare_cols)
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if name is None:
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name = OPTS.output_name
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sram_config.set_local_config(self)
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# reset the static duplicate name checker for unit tests
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# in case we create more than one SRAM
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from openram.base import design
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design.name_map=[]
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debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
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self.num_words,
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self.num_banks))
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start_time = datetime.datetime.now()
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self.name = name
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from .sram_1bank import sram_1bank as sram
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self.s = sram(name, sram_config)
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self.s.create_netlist()
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if not OPTS.netlist_only:
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self.s.create_layout()
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if not OPTS.is_unit_test:
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print_time("SRAM creation", datetime.datetime.now(), start_time)
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def sp_write(self, name, lvs=False, trim=False):
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self.s.sp_write(name, lvs, trim)
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def lef_write(self, name):
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self.s.lef_write(name)
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def gds_write(self, name):
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self.s.gds_write(name)
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def verilog_write(self, name):
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self.s.verilog_write(name)
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if self.num_banks != 1:
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from .sram_multibank import sram_multibank
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mb = sram_multibank(self.s)
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mb.verilog_write(name[:-2] + '_top.v')
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def extended_config_write(self, name):
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"""Dump config file with all options.
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Include defaults and anything changed by input config."""
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f = open(name, "w")
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var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
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for var_name, var_value in var_dict.items():
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if isinstance(var_value, str):
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f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
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else:
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f.write(str(var_name) + " = " + str(var_value)+ "\n")
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f.close()
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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# Import this at the last minute so that the proper tech file
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# is loaded and the right tools are selected
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from openram import verify
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.s.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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functional(self.s,
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os.path.basename(spname),
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cycles=200,
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output_path=OPTS.output_path)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.s.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.s.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
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debug.print_raw("LVS: Writing to {0}".format(lvsname))
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self.sp_write(lvsname, lvs=True)
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if not OPTS.netlist_only and OPTS.check_lvsdrc:
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verify.write_lvs_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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sp_name=os.path.basename(lvsname),
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("LVS writing", datetime.datetime.now(), start_time)
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# Save the extracted spice file
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if OPTS.use_pex:
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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pexname = OPTS.output_path + self.s.name + ".pex.sp"
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spname = OPTS.output_path + self.s.name + ".sp"
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verify.run_pex(self.s.name, gdsname, spname, output=pexname)
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sp_file = pexname
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print_time("Extraction", datetime.datetime.now(), start_time)
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else:
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# Use generated spice file for characterization
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sp_file = spname
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# Save a functional simulation file
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# Characterize the design
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start_time = datetime.datetime.now()
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from openram.characterizer import lib
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debug.print_raw("LIB: Characterizing... ")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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# Write the config file
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start_time = datetime.datetime.now()
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from shutil import copyfile
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copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
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debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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print_time("Config", datetime.datetime.now(), start_time)
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# Write the datasheet
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start_time = datetime.datetime.now()
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from openram.datasheet import datasheet_gen
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dname = OPTS.output_path + self.s.name + ".html"
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debug.print_raw("Datasheet: Writing to {0}".format(dname))
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datasheet_gen.datasheet_write(dname)
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print_time("Datasheet", datetime.datetime.now(), start_time)
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# Write a verilog model
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start_time = datetime.datetime.now()
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vname = OPTS.output_path + self.s.name + '.v'
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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# Write out options if specified
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if OPTS.output_extended_config:
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start_time = datetime.datetime.now()
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oname = OPTS.output_path + OPTS.output_name + "_extended.py"
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debug.print_raw("Extended Config: Writing to {0}".format(oname))
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self.extended_config_write(oname)
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print_time("Extended Config", datetime.datetime.now(), start_time)
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@@ -1,177 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log, sqrt, ceil
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from openram import debug
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from openram.sram_factory import factory
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from openram import OPTS
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class sram_config:
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""" This is a structure that is used to hold the SRAM configuration options. """
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def __init__(self, word_size, num_words, write_size=None, num_banks=1, words_per_row=None, num_spare_rows=0, num_spare_cols=0):
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self.word_size = word_size
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self.num_words = num_words
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# Don't add a write mask if it is the same size as the data word
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self.write_size_init = write_size
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if write_size:
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self.write_size = write_size
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else:
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self.write_size = word_size
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self.num_banks = num_banks
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self.num_spare_rows = num_spare_rows
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self.num_spare_cols = num_spare_cols
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try:
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from openram.tech import array_row_multiple
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self.array_row_multiple = array_row_multiple
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except ImportError:
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self.array_row_multiple = 1
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try:
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from openram.tech import array_col_multiple
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self.array_col_multiple = array_col_multiple
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except ImportError:
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self.array_col_multiple = 1
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# This will get over-written when we determine the organization
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self.words_per_row = words_per_row
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self.compute_sizes()
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def __str__(self):
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""" override print function output """
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config_items = ["num_banks",
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"word_size",
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"num_words",
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"words_per_row",
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"write_size",
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"num_spare_rows",
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"num_spare_cols"]
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str = ""
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for item in config_items:
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val = getattr(self, item)
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str += "{} : {}\n".format(item, val)
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return str
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def set_local_config(self, module):
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""" Copy all of the member variables to the given module for convenience """
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members = [attr for attr in dir(self) if not callable(getattr(self, attr)) and not attr.startswith("__")]
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# Copy all the variables to the local module
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for member in members:
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setattr(module, member, getattr(self, member))
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def compute_sizes(self):
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""" Computes the organization of the memory using bitcell size by trying to make it square."""
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bitcell = factory.create(module_type=OPTS.bitcell)
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debug.check(ceil(log(self.num_banks, 2)) == log(self.num_banks, 2) ,
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"Number of banks should be power of 2.")
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self.num_words_per_bank = self.num_words / self.num_banks
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self.num_bits_per_bank = self.word_size * self.num_words_per_bank
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# If this was hard coded, don't dynamically compute it!
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if not self.words_per_row:
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# Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry)
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self.bank_area = bitcell.width * bitcell.height * self.num_bits_per_bank
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self.bank_side_length = sqrt(self.bank_area)
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# Estimate the words per row given the height of the bitcell and the square side length
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self.tentative_num_cols = int(self.bank_side_length / bitcell.width)
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self.words_per_row = self.estimate_words_per_row(self.tentative_num_cols, self.word_size)
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# Estimate the number of rows given the tentative words per row
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self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row * self.word_size)
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self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
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self.recompute_sizes()
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# Set word_per_row in OPTS
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OPTS.words_per_row = self.words_per_row
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debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row))
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def recompute_sizes(self):
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"""
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Calculate the auxiliary values assuming fixed number of words per row.
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This can be called multiple times from the unit test when we reconfigure an
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SRAM for testing.
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"""
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debug.info(1, "Recomputing with words per row: {}".format(self.words_per_row))
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# If the banks changed
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self.num_words_per_bank = self.num_words / self.num_banks
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self.num_bits_per_bank = self.word_size * self.num_words_per_bank
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# Fix the number of columns and rows
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self.num_cols = int(self.words_per_row * self.word_size)
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self.num_rows_temp = int(self.num_words_per_bank / self.words_per_row)
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self.num_rows = self.num_rows_temp + self.num_spare_rows
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debug.info(1, "Rows: {} Cols: {}".format(self.num_rows_temp, self.num_cols))
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# Fix the write_size
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if self.write_size_init:
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self.write_size = self.write_size_init
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else:
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self.write_size = self.word_size
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# Compute the address and bank sizes
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self.row_addr_size = ceil(log(self.num_rows, 2))
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self.col_addr_size = int(log(self.words_per_row, 2))
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self.bank_addr_size = self.col_addr_size + self.row_addr_size
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self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
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#self.addr_size = self.bank_addr_size
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debug.info(1, "Row addr size: {}".format(self.row_addr_size)
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+ " Col addr size: {}".format(self.col_addr_size)
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+ " Bank addr size: {}".format(self.bank_addr_size))
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num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
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if num_ports == 1:
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if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0):
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debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, self.array_col_multiple), -1)
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if ((self.num_rows + num_ports) % self.array_row_multiple != 0):
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debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, self.array_row_multiple), -1)
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def estimate_words_per_row(self, tentative_num_cols, word_size):
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"""
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This provides a heuristic rounded estimate for the number of words
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per row.
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"""
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tentative_column_ways = tentative_num_cols / word_size
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column_mux_sizes = [1, 2, 4, 8, 16]
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# If we are double, we may want a larger column mux
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if tentative_column_ways > 2 * column_mux_sizes[-1]:
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debug.warning("Extremely large number of columns for 16-way maximum column mux.")
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closest_way = min(column_mux_sizes, key=lambda x: abs(x - tentative_column_ways))
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return closest_way
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def amend_words_per_row(self, tentative_num_rows, words_per_row):
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"""
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This picks the number of words per row more accurately by limiting
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it to a minimum and maximum.
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"""
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# Recompute the words per row given a hard max
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if(not OPTS.is_unit_test and tentative_num_rows > 512):
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debug.check(tentative_num_rows * words_per_row <= 4096,
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"Number of words exceeds 2048")
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return int(words_per_row * tentative_num_rows / 512)
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# Recompute the words per row given a hard min
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if (not OPTS.is_unit_test and tentative_num_rows < 16):
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debug.check(tentative_num_rows * words_per_row >= 16,
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"Minimum number of rows is 16, but given {0}".format(tentative_num_rows))
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return int(words_per_row * tentative_num_rows / 16)
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return words_per_row
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