diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py
index bc2b1741..cb9c9909 100644
--- a/compiler/pgates/single_level_column_mux.py
+++ b/compiler/pgates/single_level_column_mux.py
@@ -10,20 +10,20 @@ class single_level_column_mux(design.design):
     """
     This module implements the columnmux bitline cell used in the design.
     Creates a single columnmux cell with the given integer size relative
-    to minimum size. Default is 2x.
+    to minimum size. Default is 8x. Per Samira and Hodges-Jackson book:
+    Column-mux transistors driven by the decoder must be sized for optimal speed
     """
 
     # This is needed for different bitline spacings
     unique_id = 1
     
-    def __init__(self, tx_size=2, bitcell_bl="bl", bitcell_br="br"):
+    def __init__(self, tx_size=8, bitcell_bl="bl", bitcell_br="br"):
         self.tx_size = int(tx_size)
         name="single_level_column_mux_{}_{}".format(self.tx_size,single_level_column_mux.unique_id)
         single_level_column_mux.unique_id += 1
         design.design.__init__(self, name)
         debug.info(2, "create single column mux cell: {0}".format(name))
 
-        self.tx_size = tx_size
         self.bitcell_bl = bitcell_bl
         self.bitcell_br = bitcell_br