From 5cf50b333a802e819d47b057f7c68b7effcd4f5b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 21 Aug 2023 20:25:51 -0700 Subject: [PATCH] bitcell array passing --- technology/sky130/custom/sky130_bitcell_base_array.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/technology/sky130/custom/sky130_bitcell_base_array.py b/technology/sky130/custom/sky130_bitcell_base_array.py index 07d187ed..68814d65 100644 --- a/technology/sky130/custom/sky130_bitcell_base_array.py +++ b/technology/sky130/custom/sky130_bitcell_base_array.py @@ -93,8 +93,8 @@ class sky130_bitcell_base_array(bitcell_base_array): if "VGND" in inst.mod.pins: self.copy_layout_pin(inst, "VGND", "gnd") - for row in range(self.pattern.row_max+1): - inst = self.all_inst[row,0] + for col in range(self.column_size): + inst = self.cell_inst[0,col] pin = inst.get_pin("vpb") self.objs.append(geometry.rectangle(layer["nwell"], pin.ll(),