From 5c4df2410e8d0f569c53d3d80cf79b1b442cb79b Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 Jun 2019 15:06:04 -0700 Subject: [PATCH] Fix dummy row LVS issue --- compiler/bitcells/dummy_bitcell.py | 48 ++++++++++++++++++ .../scn4m_subm/gds_lib/dummy_cell_6t.gds | Bin 0 -> 5608 bytes .../scn4m_subm/mag_lib/dummy_cell_6t.mag | 11 ++-- technology/scn4m_subm/mag_lib/setup.tcl | 1 + technology/scn4m_subm/sp_lib/dummy_cell_6t.sp | 5 +- 5 files changed, 57 insertions(+), 8 deletions(-) create mode 100644 compiler/bitcells/dummy_bitcell.py create mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_6t.gds diff --git a/compiler/bitcells/dummy_bitcell.py b/compiler/bitcells/dummy_bitcell.py new file mode 100644 index 00000000..db748203 --- /dev/null +++ b/compiler/bitcells/dummy_bitcell.py @@ -0,0 +1,48 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +import debug +import utils +from tech import GDS,layer,parameter,drc +import logical_effort + +class dummy_bitcell(design.design): + """ + A single bit cell (6T, 8T, etc.) This module implements the + single memory cell used in the design. It is a hand-made cell, so + the layout and netlist should be available in the technology + library. + """ + + pin_names = ["bl", "br", "wl", "vdd", "gnd"] + (width,height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"]) + + def __init__(self, name=""): + # Ignore the name argument + design.design.__init__(self, "dummy_cell_6t") + debug.info(2, "Create dummy bitcell") + + self.width = dummy_bitcell.width + self.height = dummy_bitcell.height + self.pin_map = dummy_bitcell.pin_map + + def analytical_power(self, corner, load): + """Bitcell power in nW. Only characterizes leakage.""" + from tech import spice + leakage = spice["bitcell_leakage"] + dynamic = 0 #temporary + total_power = self.return_power(dynamic, leakage) + return total_power + + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width. + access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] + return 2*access_tx_cin diff --git a/technology/scn4m_subm/gds_lib/dummy_cell_6t.gds b/technology/scn4m_subm/gds_lib/dummy_cell_6t.gds new file mode 100644 index 0000000000000000000000000000000000000000..d17cdd3bbb1c66e5cf011be20d23bf69521dc067 GIT binary patch literal 5608 zcmbuDJ#1V>6os$7_Il%NoVDX$Y~m%sN&LgG&Y(Z~c8^8k zC@w6%SN(65ezS!qk^9yClD9gci$1oDzu*7+#3!|3*6x+Ox)-|W?HNCw=-cjz5r>%Z zDfFy=dOi9ve)_|!duHfjUH<9y$h+`Fj5vy$+N=5Rmh}tI@@C`}SqthSx?bylWyh@1 zH4~RN6*uU5#&0%p96siaA2JSfG4GG~)QSA!+)3!7>)HJ5AAG7ioI8pABM$lBEbC{s zWM(%WnXPn7uJu9}y}g>h;_vtW@%$^NvH!$X-&5$K>-B!mJ+c#HD0r&4iQSyv>{1## z`=2=!^zjtBSmS4(F>bu#>PGBeF+cw3hj;ct#3<~ z)<1I?{iq%N;Z(;AU98JLa~OF!Ym9?4Lmb6T?bZD21Lx<+?B?w_>*DJNUN_f8*R%fC zuGwYpKj|^VE1#L6i>_z=*Pe%OZm}djbTRMm_xtxFw;h$dd=R?mW6S1eo{XKlPGlbF zVx7OWt1*aXjD`6J3q70v+Vk+uEsEh|{`gaS#vdNeJ$=RN&q5c6&i}yrGiQ9vRlNQz zY9ZG7r~eEeWq*2i}=vRyg%kiF6J+)rlRYa`b8dmbjpE>iP)*^Qo-$nnP^-~|-AMlHKQ{4)>Uh8M<#eJJd z9L0s+UhC(*k@XXamwW|>-X90*&mGq|jroe)-{_+2+5Gb_A}{Mkeyt-q>yX+r{&;4L zZu;5lnu(3{{vx_w_1~-R|8_6l)p%C%E(ghrF1nue^Xz85wAPSwh%S12)=$3bTCsMl z1-j_%RsXxgLspjgf6FhkBrkb$;$`YF*q{iNrz|y*)GjsLv(ONBzX5qtHdyGycfK86CJkeH@pJYR2c3ASJ?rO=Kl)aGe_=0=?Z=)@?V0@4IQ-S$Kk!rgV9{Rnzc+Y)g@0s6 zG}FBmtn-)S*Y9EMo3&nyKUnW)-*HcH{zQD}qU)LQ#~x>%>>m*ydtY=t>;HfCf-UP^V+U8mzrN~=SRn108+0X2737!DCfZ6uKXRrV?9l= JCVVDi_Ah|$OXvUq literal 0 HcmV?d00001 diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag index f2e9906a..c1b14848 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1536091415 +timestamp 1560540221 << nwell >> rect -8 29 42 51 << pwell >> @@ -92,17 +92,18 @@ rect 32 16 36 22 rect -2 6 17 9 rect 21 6 36 9 rect -2 5 36 6 +rect 6 -2 10 2 +rect 20 -2 24 2 << m2contact >> rect 15 44 19 48 rect -2 29 2 33 rect 32 29 36 33 -rect 6 -2 10 2 -rect 20 -2 24 2 << metal2 >> rect -2 33 2 48 rect -2 -2 2 29 -rect 6 2 10 48 -rect 24 -2 28 48 +rect 6 -2 10 48 +rect 24 2 28 48 +rect 20 -2 28 2 rect 32 33 36 48 rect 32 -2 36 29 << bb >> diff --git a/technology/scn4m_subm/mag_lib/setup.tcl b/technology/scn4m_subm/mag_lib/setup.tcl index 01639fe2..2ba148b5 100644 --- a/technology/scn4m_subm/mag_lib/setup.tcl +++ b/technology/scn4m_subm/mag_lib/setup.tcl @@ -4,6 +4,7 @@ equate class {-circuit1 nfet} {-circuit2 n} equate class {-circuit1 pfet} {-circuit2 p} # This circuit has symmetries and needs to be flattened to resolve them # or the banks won't pass +flatten class {-circuit1 dummy_cell_6t} flatten class {-circuit1 bitcell_array_0} flatten class {-circuit1 bitcell_array_1} #flatten class {-circuit1 precharge_array_0} diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp index ea939036..3b0584df 100644 --- a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp +++ b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp @@ -1,7 +1,6 @@ -*********************** "cell_6t" ****************************** -.SUBCKT cell_6t bl br wl vdd gnd -* SPICE3 file created from cell_6t.ext - technology: scmos +*********************** "dummy_cell_6t" ****************************** +.SUBCKT dummy_cell_6t bl br wl vdd gnd * Inverter 1 M1000 Q Qbar vdd vdd p w=0.6u l=0.8u