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Remove unnecessary imports
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@@ -14,7 +14,6 @@ from openram.base import rom_verilog
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from openram import OPTS, print_time
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from openram.sram_factory import factory
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from openram.tech import drc, layer, parameter
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from openram.router import router_tech
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class rom_bank(design,rom_verilog):
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@@ -14,7 +14,6 @@ from openram.base import channel_route
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from openram.base import design
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from openram.base import verilog
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from openram.base import lef
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from openram.router import router_tech
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from openram.sram_factory import factory
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from openram.tech import spice
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from openram import OPTS, print_time
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