diff --git a/compiler/modules/rom_bank.py b/compiler/modules/rom_bank.py
index 7cf30dc3..74d0678b 100644
--- a/compiler/modules/rom_bank.py
+++ b/compiler/modules/rom_bank.py
@@ -14,7 +14,6 @@ from openram.base import rom_verilog
 from openram import OPTS, print_time
 from openram.sram_factory import factory
 from openram.tech import drc, layer, parameter
-from openram.router import router_tech
 
 
 class rom_bank(design,rom_verilog):
diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py
index 843d13d8..c4f8dc28 100644
--- a/compiler/modules/sram_1bank.py
+++ b/compiler/modules/sram_1bank.py
@@ -14,7 +14,6 @@ from openram.base import channel_route
 from openram.base import design
 from openram.base import verilog
 from openram.base import lef
-from openram.router import router_tech
 from openram.sram_factory import factory
 from openram.tech import spice
 from openram import OPTS, print_time
diff --git a/compiler/router/__init__.py b/compiler/router/__init__.py
index cb521a12..ac2a64ec 100644
--- a/compiler/router/__init__.py
+++ b/compiler/router/__init__.py
@@ -3,6 +3,5 @@
 # Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
-from .router_tech import *
 from .signal_escape_router import *
 from .supply_router import *