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scmos array connecting

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This commit is contained in:
Jesse Cirimelli-Low
2023-07-25 15:02:06 -07:00
parent cb21443e2d
commit 4cf3ea91ff
2 changed files with 21 additions and 7 deletions
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compiler/modules/bitcell_array.py
+9 -1
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@@ -79,7 +79,15 @@ class bitcell_array(bitcell_base_array):
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, mirror="MX")
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, mirror="MY")
core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, mirror="XY")
self.pattern = pattern(self, "bitcell_array", core_block, self.row_size/2, self.column_size/2)
num_core_x = self.row_size/len(core_block[0])
num_core_y = self.column_size/len(core_block)
debug.check(num_core_x.is_integer(), "number of core blocks must be an integer")
debug.check(num_core_y.is_integer(), "number of core blocks must be an integer")
num_core_x = int(num_core_x)
num_core_y = int(num_core_y)
self.pattern = pattern(self, "bitcell_array", core_block, num_core_x, num_core_y)
self.pattern.connect_array()
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""