From 4cf3ea91ff2e96c6a92446c2c40c9a6b3c7a7cd4 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 25 Jul 2023 15:02:06 -0700
Subject: [PATCH] scmos array connecting

---
 compiler/modules/bitcell_array.py | 10 +++++++++-
 compiler/modules/pattern.py       | 18 ++++++++++++------
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 10e57747..624bd4ac 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -79,7 +79,15 @@ class bitcell_array(bitcell_base_array):
         core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, mirror="MX")
         core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, mirror="MY")
         core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, mirror="XY")
-        self.pattern = pattern(self, "bitcell_array", core_block, self.row_size/2, self.column_size/2)
+        num_core_x = self.row_size/len(core_block[0])
+        num_core_y = self.column_size/len(core_block)
+        debug.check(num_core_x.is_integer(), "number of core blocks must be an integer")
+        debug.check(num_core_y.is_integer(), "number of core blocks must be an integer")
+        num_core_x = int(num_core_x)
+        num_core_y = int(num_core_y)
+
+        self.pattern = pattern(self, "bitcell_array", core_block, num_core_x, num_core_y)
+        self.pattern.connect_array()
 
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
diff --git a/compiler/modules/pattern.py b/compiler/modules/pattern.py
index d0320f13..c45c4e49 100644
--- a/compiler/modules/pattern.py
+++ b/compiler/modules/pattern.py
@@ -40,11 +40,13 @@ class pattern():
         self.parent_design = parent_design
         self.name = name
         self.core_block = core_block
+        self.num_core_x = num_core_x
+        self.num_core_y = num_core_y
+        self.cores_per_x_block = cores_per_x_block
+        self.cores_per_y_block = cores_per_y_block
         self.x_block = x_block
         self.y_block = y_block
         self.xy_block = xy_block
-        self.cores_per_x_block = cores_per_x_block
-        self.cores_per_y_block = cores_per_y_block
         self.initial_x_block = initial_x_block
         self.initial_y_block = initial_y_block
         self.final_x_block = final_x_block
@@ -99,7 +101,6 @@ class pattern():
         for dy in range(len(block)):
             for dx in range(len(block[0])):
                 inst = block[dy][dx]
-                print(inst.name)
                 self.parent_design.cell_inst[x + dx, y + dy] = self.parent_design.add_existing_inst(inst)
                 self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(x+dx, y+dy))
 
@@ -107,9 +108,14 @@ class pattern():
     def connect_array(self) -> None:
         x = 0
         y = 0
-        self.connect_block(self.core_block, x,y)
-
-        
+        for i in range(self.num_core_y):
+            for j in range (self.num_core_x):
+                print("connecting {} {}".format(x,y))
+                self.connect_block(self.core_block, x,y)
+                x += len(self.core_block[0])
+            x = 0
+            y += len(self.core_block)
+    
     def place_array(self) -> None:
 
         array_x = 0