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fix col_cap array for dummu compatability ...bitcells next

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This commit is contained in:
Jesse Cirimelli-Low
2025-03-06 02:05:43 -08:00
parent f3c1c5fbb2
commit 4ce6e0538b
7 changed files with 32 additions and 19 deletions
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compiler/modules/capped_replica_bitcell_array.py
+6 -2
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@@ -87,7 +87,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
# dummy column + left replica column(s)
column_offset=0,
mirror=0,
location="top")
location="top",
left_rbl=self.left_rbl,
right_rbl=self.right_rbl)
self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
cols=self.column_size + len(self.rbls),
@@ -95,7 +97,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
# dummy column + left replica column(s)
column_offset=0,
mirror=0,
location="bottom")
location="bottom",
left_rbl=self.left_rbl,
right_rbl=self.right_rbl)
# Dummy Col or Row Cap, depending on bitcell array properties
row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")
compiler/modules/col_cap_array.py
+1 -1
View File
@@ -12,7 +12,7 @@ class col_cap_array(bitcell_base_array):
"""
Generate a dummy row/column for the replica array.
"""
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="",left_rbl=[],right_rbl=[]):
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
self.mirror = mirror
self.location = location
compiler/modules/pattern.py
-3
View File
@@ -176,9 +176,6 @@ class pattern():
self.parent_design.all_inst[row, col] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col))
self.parent_design.connect_inst(self.parent_design.get_strap_pins(self.bit_rows[col], self.bit_cols[row]))
def print_bit_blocck():
return
def place_inst(self, inst, offset) -> None:
x = offset[0]
y = offset[1]